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I'm designing a SEPIC converter based on a wide input voltage range SMPS controller (LTC3758). The requirement is for a wide input voltage (10-60V) with a fixed output of 28V @ 1.5A. I'm trying to determine Cout selection which per the data sheet, is the same for a SEPIC converter as it is a Boost converter.

I've calculated an output ripple current of around 2.4A which appears difficult to achieve using electrolytics in a small form factor and given I require an output capacitance of 17uF I would like to use ceramics.

Electrolytic's often have a ripple current rating specification in their data sheet however, ceramics seem to not. Is this due to their inherently low ESR, and if so, how does one determine if a ceramic capacitor of an appropriate voltage rating and capacitance is suitable?

For example I've found a particular X7R 10uF 35V ceramic cap - how can I determine the ripple currents effect on it's performance?

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    \$\begingroup\$ Frequency and capacitance influence voltage ripple as the other equations in the datasheet suggest. The capacitor RMS current only depends on the output current and duty cycle, so i think the datasheet is correct. Why do you think 2.4A is high and problematic for SMD caps? \$\endgroup\$ Commented Aug 1, 2021 at 7:07
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    \$\begingroup\$ Thanks @LarsHankeln, I've updated my question to better represent the problem I'm trying to solve. Ultimately what I don't understand is why ceramic caps don't have a ripple current rating and what the limits are. Say, if I had a circuit with 100A of ripple current and a requirement for 10uF, surely a 1210 would fail. How does one determine when this happens (and why)? \$\endgroup\$ Commented Aug 3, 2021 at 11:07
  • \$\begingroup\$ As a first estimate the thermal dissipation of ESR x I^2 / 8 will be one limit for ripple current. If you assume half a Watt for a 1210 and an ESR of 10 mohm you can guess 20 A of peak to peak ripple current. \$\endgroup\$
    – tobalt
    Commented Aug 3, 2021 at 11:47
  • \$\begingroup\$ @AlexTurner I posted about ripple current for ceramics some time ago: electronics.stackexchange.com/questions/542464/… \$\endgroup\$ Commented Aug 3, 2021 at 12:37

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Ceramic capacitors are really quite rugged. They behave (and fail) like a piece of wire when ripple current is applied: The current heats the capacitor via its ESR and if it gets too hot, it gets damaged.

Let's take the C5750X7S2A106K230KB from TDK as an example. This is a 10µF 100V X7S capacitor in a 2220 form factor. TDK very helpfully provides characteristic data for this capacitor.

Looking at the "temperature rise characteristics" in the characteristics sheet, you'll see that this capacitor can take about 4A at 100kHz for its temperature to rise by 20°C. This doesn't mean that that's the maximum the cap can take, however: The relationship between ripple current and temperature rise is quadratic, as in P=I²R. If you're okay with a 45°C temperature rise (or can provide cooling to the capacitor by means of large copper pours on the PCB), you can push it to 6A.

Another thing to keep in mind is the capacitor's DC bias characteristics: Even though this capacitor is advertised as "10µF", it'll drop to about 6µF at 30V already. This means that you'll need three of those in parallel to reach your required 17µF, not just two. Characteristic sheets are really the only way to figure this out, which is why I stay far away from ceramic caps that don't provide this data. I wouldn't be surprised if your 10µF 35V cap drops to something ridiculous like 2µF when you apply your 28V to it.

An Aluminum Polymer capacitor, like the 50SEK22M from Panasonic, might be a better option. They're much cheaper than ceramics for this capacitance range and can take a lot of ripple current too. Don't forget to add a small ceramic cap in parallel, on the order of 100nF, to improve high-frequency filtering. (This cap doesn't have to take much ripple current. The current is shared in proportion to the capacitances, so about 0.5% of it goes through the parallel 100nF cap. This is negligible.)

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    \$\begingroup\$ I believe a general advice of adding a small cercap beside a bank of Al polys runs the risk of significant ringing due to LC. it can be alright, if the polys have sufficient ESR, but I wouldnt do it without a simulation. \$\endgroup\$
    – tobalt
    Commented Aug 3, 2021 at 14:44

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