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I'm designing a substantial (200W) buck converter with the LT3840 (datasheet) controller (but the question is not really part specific). As usual with these parts the datasheet says:

  • Minimize the hot loop. (See Figure 9 [the power current loop])
  • Use short wide traces for the MOSFET gate drivers (TG and BG), as well as, gate drive supply and return (INTVCC and BOOST, BGRTN and SW) [the gate drive loop].

They also give a reference design which is actually quite interesting:

Reference layout Full gerbers/design

Looking for example at Q3-Q4 the gates are brought down with two vias and then routed to the controller in a big trace (it's 1mm wide on a 70µm copper layer). Of course this is done to minimize trace inductance and resistance given the huge gates these MOSFET have and the potential switching frequency (it can go up to 1MHz).

However this power stage is almost too much compact… the thermal performance for the devices is usually given for a square inch of copper (usually single sided, if they use the JEDEC test coupon). In these condition they are working almost in their minimal footprint condition with some difficult to estimate improvement due to the four layers and thermal vias. Outer planes have something like 5×8mm for each MOSFET but the internal planes are almost solid copper and that helps a lot.

Now, my MOSFETs here have a RthJA of 50°C/W with a the square inch copper (they are 5×6); they don't even quote the minimal footprint condition since it would be probably huge. I can't afford a four layer and I don't really think that a dual 70µm layer copper board in almost minimal footprint could reach that. If I really had to guess probably it would be about 75°C/W.

My idea was to spread the packages and add more radiant copper. I'm running at a quite low frequency (200kHz) to minimize switching losses (I'm trading inductance with ripple for the switching inductor, the resulting cost is the same) but, ideally, the last MOSFET would be at something like 70mm from the controller which doesn't fit in my description of ``short trace'', even when 1mm wide.

Is there some quantitative estimate for a limit? I was thinking of estimating the resulting gate trace impedance and compare it with the output driver one. If the resulting value is ``well below'' of the driver output resistance (say, less than 5-10%), the driver should work fine, right?

What could be the penalty except for a raise in switching losses?

EDIT: I'm trying to look at it from a different angle, as a signal integrity problem (if the drive power reflects, the switching losses rise since the gate doesn't get charged fast enough):

First order huge approximation: the nominal transition time of the LT3840 is 20ns; using the 0.35/t approximation the signal bandwidth is of about 18MHz. Using as conventional propagation speed half c for FR4 (150E6 m/s) I get a wavelength of about 8mm.

By conventional wisdom over 5-10 times the wavelength a trace is better considered as a transmission line. Ouch. I guess that the resulting 75mm gate trace is electrically long (even worse, it's split between two gates so there are stubs effects)

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    \$\begingroup\$ Good question. I would examine the ESL/ ESR ratio for all contributors of Ron, DCR, ESR and trace inductance and compare with rise time to compute the C load for Q and reactive power increase that will increase switching losses in the FET with voltage and current phase shift Vs the differences in Rth from a larger cooling effect. My gut feeling is reducing reactance and impedance mismatching is far more important than a slight reduction in Rth. if tR / 200kHz > 5% then you have at least 20 x the BW/fs ratio which raises ESL impedance by the same. \$\endgroup\$ Commented Aug 2, 2021 at 12:49
  • \$\begingroup\$ I would use the practise of conjugate impedance matching for interfaces as a goal with damping to lower Q. \$\endgroup\$ Commented Aug 2, 2021 at 12:56
  • \$\begingroup\$ Please link the data sheet and the reference design you mention of which you extracted the picture. \$\endgroup\$
    – Andy aka
    Commented Aug 2, 2021 at 14:15
  • \$\begingroup\$ From estimates this converter losses (at least on MOSFETs) are on switching so I'm quite worried on the effect; the Q approach seems interesting however I'm not familiar with it, do you have some pointers? I usually treat gates simply as 'capacitor to charge' quickly enough, not as reactive load; I only did a couple of RF matchings so it's not my field of expertise. I guess the idea is that if the 'gate wave' is reflected by the MOSFET input it simply dissipates in the gate driver (and doesn't charge the gate raising the losses). Am I correct? \$\endgroup\$ Commented Aug 3, 2021 at 7:32
  • \$\begingroup\$ Did some estimation in the edit. At 20ns rise the gate drive trace becomes a transmission line. Even worse than I expected \$\endgroup\$ Commented Aug 3, 2021 at 8:24

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I have some experience with Linear's high-speed gate drivers. The driver in the LT3840 appears to be quite similar to the LTC4442 discrete half-bridge driver; both of them feature shoot-through protection.

Do not, under any circumstances, make the gate drive traces longer than absolutely necessary. I had once made a PCB with a LTC4442 and 20mm gate drive traces to get to the gates of a pair of less-than-ideally oriented DPAK FETs. This was enough to cause the LTC4442's shoot-through protection circuitry to oscillate, resulting in the gate driver destroying itself within a few seconds of continued operation. The solution to this was to switch to much smaller MOSFET packages that were additionally oriented in such a way that the LTC4442's outputs were right next to their gate pins, shortening the gate drive traces to about 4 millimeters.

These gate drivers are also incredibly sensitive to supply voltage decoupling. On an earlier attempt, a LTC4442 blew up(!) because the decoupling capacitor was placed about 8mm away from the chip for layouting reasons. The resulting transients from the high current switching events flat-out killed the chip.

If thermals are an issue, you're better off sticking small heatsinks to your FETs with thermal adhesive tape rather than making the gate drive traces longer. If heatsinks aren't an option, you could try using SMD thermal jumpers to conduct some heat away from your FETs to a ground or power plane.

TL;DR: Sacrifice everything to make the gate drivers happy.

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  • \$\begingroup\$ I fully believe you… on a TI DC-DC regulator (a companion chip for their bluetooth) I had hiccup regulation (i.e. it didn't work) because the bypass cap trace was 0.75mm longer than the one in the demo board. TI confirmed that the demo layout was essentially the only way to make it work. Given that Linear built a whole aux booster for this gate driver part it would me surprise it would be tuned for really high performances. I'd look at the discrete part you mentioned too, maybe it has some insight, thanks \$\endgroup\$ Commented Aug 3, 2021 at 14:46
  • \$\begingroup\$ By the way the older IRF gate drivers (before they added UV lockup) had the same blow-up behaviour. Technical support: it's on the datasheet, it isn't supposed to work with less than the minimum on the supply pin:P For cooling I'm thinking about a bottom spreader, there should be plenty of metal to dump heat near that board. Also I've a lot of aluminum sinks to try (we have our local Aavid/Fischer equivalent on speed dial). \$\endgroup\$ Commented Aug 3, 2021 at 14:50

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