The instruction is not sent to a register in the assembly-programming sense, i.e. one that has a name and is programmer-accessible (e.g. r2, lr, sp, pc, etc).
However, it is very likely to be stored in a register in the digital logic design sense of the term, i.e. an array of flip-flops or other storage elements with a common clock and enable. This is called the instruction register.
In the Cortex-M3, the IR stores the fetched instruction before it is decoded by the next stage. A more advanced architecture with out-of-order execution may have multiple IRs feeding multiple decoders. For example, Intel Sandy Bridge has an entire instruction queue rather than a single IR, which feeds four decoders that yield uops to the post-decode/allocation queue, architectural register renamer, and scheduler. Instructions are being stored in registers of all different types, in all different formats, in these stages.