As far as I understood, the fetched "data"(not instruction) is first loaded to one of the CPU registers.

But in case of a single "instruction"(not data) fetched from the memory, is this instruction is sent to one of the CPU registers first or is it immediately sent to control unit to be decoded?

(I'm mostly talking about cortex M3 and M4 if it matters)

  • \$\begingroup\$ Clearly the instruction must be somewhere while its decoded. Where else could it be except a register? That's almost certainly a dedicated instruction register, and not one of the general purpose data registers available to the programmer. \$\endgroup\$
    – user4574
    Aug 2, 2021 at 18:37
  • \$\begingroup\$ Is the instruction first sent to the instruction register and then to the Control Unit to be decoded? Or is the instruction sent to instruction register and the Control Unit at the same time? \$\endgroup\$
    – user1999
    Aug 2, 2021 at 18:39
  • 1
    \$\begingroup\$ It depends on the cpu architecture \$\endgroup\$
    – Mitu Raj
    Aug 2, 2021 at 18:50
  • 2
    \$\begingroup\$ I would say that the instruction register is part of the Control Unit - or that the two things are so closely coupled that they may be considered as a single unit. \$\endgroup\$ Aug 2, 2021 at 19:28

1 Answer 1


The instruction is not sent to a register in the assembly-programming sense, i.e. one that has a name and is programmer-accessible (e.g. r2, lr, sp, pc, etc).

However, it is very likely to be stored in a register in the digital logic design sense of the term, i.e. an array of flip-flops or other storage elements with a common clock and enable. This is called the instruction register.

In the Cortex-M3, the IR stores the fetched instruction before it is decoded by the next stage. A more advanced architecture with out-of-order execution may have multiple IRs feeding multiple decoders. For example, Intel Sandy Bridge has an entire instruction queue rather than a single IR, which feeds four decoders that yield uops to the post-decode/allocation queue, architectural register renamer, and scheduler. Instructions are being stored in registers of all different types, in all different formats, in these stages.

  • \$\begingroup\$ So is the instruction first sent to instruction register and then to the Control Unit to be decoded? Or is the instruction sent to instruction register and the Control Unit at the same time? \$\endgroup\$
    – user1999
    Aug 2, 2021 at 18:39
  • \$\begingroup\$ There may be no single answer to that : the Control Unit probably has a register as part of its input. It may also depend on the specific ARM revision; faster ones may be more deeply pipelined and have more registers not visible to the ISA. \$\endgroup\$
    – user16324
    Aug 2, 2021 at 18:46
  • \$\begingroup\$ @user1999 The IR is a part of the control unit, and it's not quite as simple as you assume. Here's a doc for the Cortex M3 - the instruction is fetched, and gets stored in a register to be decoded on the next clock cycle. Following that, the decoded control signals are likely themselves registered before being sent to the execute stages. \$\endgroup\$
    – nanofarad
    Aug 2, 2021 at 18:48
  • \$\begingroup\$ @user_1818839 Sending to the control unit and sending to the instruction register means the same thing. Normally as a CPU designer you'd consider the instruction register as part of the control unit. The instruction register is basically the decoder's memory \$\endgroup\$
    – slebetman
    Aug 3, 2021 at 4:13
  • \$\begingroup\$ @user_1818839 Note that for real CPUs it's more complex than this as the instruction decoder does not fetch instructions from RAM directly. Instead instructions are fetched from cache. This may be general cache or in some cases it may be a dedicated instruction cache (making the CPU core a mini Harvard architecture). In some cases a dual-ported instruction cache means you don't need a separate instruction register for the decoder to work as you can attach the decoder directly to the cache output \$\endgroup\$
    – slebetman
    Aug 3, 2021 at 4:17

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