From what I know, it takes roughly these steps to read DRAM data:
- Enable RAS signal, send the row address
- Wait for some Time(
tRCD), then enable CAS signal, send the column address and read command
- Wait for another some time(
CL), then get what we need.
CAS Latency (CL) is the best known memory parameter
CL just means the latency between column selection and sending data, I don't understand why
tRCD often gets ignored.