# Why is CAS latency mostly recognized in DRAM timing?

From what I know, it takes roughly these steps to read DRAM data:

• Enable RAS signal, send the row address
• Wait for some Time(tRCD), then enable CAS signal, send the column address and read command
• Wait for another some time(CL), then get what we need.

So Basically, tRCD and CL should be the same importance because we have to wait both. But many resources, such as this and this, claiming that

CAS Latency (CL) is the best known memory parameter

Since CL just means the latency between column selection and sending data, I don't understand why tRCD often gets ignored.

• best known doesn't mean important. it just because the parameter ricers used to quote on stuff when comparing RAM. Aug 4 '21 at 9:35
• No designer ignores timing parameters of DRAM. Aug 4 '21 at 9:51
• Having addressed a row, you can access multiple columns within it, fast. For systems optimised to do that, CAS latency is what matters most. That's all. Any systems that don't do that are low performance by definition. Aug 4 '21 at 13:20

## 1 Answer

Two reasons:

• If you actually look at the DRAM datasheet, you'll see that tCL is the largest component of the overall access time.

• In any but the most primitive DRAMs, there are advanced access modes (burst mode, fast page mode, etc.) that eliminate the need to cycle RAS for every access. This means that tCL is the only component left of the overall access time.

And especially with modern SDRAM, the row and column addresses are provided on consecutive clock cycles, while the data isn't returned until some 10-20 clock cycles later. Again, tCL is the primary determiner of memory random-read performance.

• with modern SDRAM, the row and column addresses are provided on consecutive clock cycles Does it mean tRCD is 0 in this case? If so, what's the point of tRCD in modern DRAM? Aug 4 '21 at 17:40
• @user239216 no, it would mean tRCD = 1 clock period. Aug 4 '21 at 20:12
• @user_1818839 I didn't see a memory module that have tRCD = 1 on its tag. Mine is 16-18-18-38, much higher than 1. Could you provide an example? Aug 5 '21 at 1:42
• No I cannot; I was merely explaining that IF the addresses were on successive clock cycles, it would not mean tRCD = 0. Aug 5 '21 at 12:25