5
\$\begingroup\$

In a JFET, is the gate always connected to the bulk/substrate ? Or is there "no rule" (sometimes it is, sometimes it is not)?

And what about the case of the MOSFET ?

enter image description here

\$\endgroup\$
10
  • 2
    \$\begingroup\$ Mosfet gates are floating \$\endgroup\$
    – tobalt
    Aug 5 at 17:12
  • \$\begingroup\$ @tobalt : apologizes : what does it mean "floating" : are there connected or not connected ? \$\endgroup\$ Aug 5 at 17:15
  • 1
    \$\begingroup\$ Do you mean Source connected to Substrate? Because Gate connected to Substrate makes no sense. You could not control the transistor. \$\endgroup\$
    – Justme
    Aug 5 at 17:15
  • \$\begingroup\$ @Justme ; I really mean "is Gate connected to substrate" (no typo) \$\endgroup\$ Aug 5 at 17:15
  • 2
    \$\begingroup\$ From Elliott and nanofarad's comments: I think you need to clarify on the question, what do you actually mean by 'connected'. \$\endgroup\$
    – Mitu Raj
    Aug 5 at 19:14
9
\$\begingroup\$

When a JFET is produced using the common planar process, the channel is first diffused into the bulk and, in order to insulate this region from it, the bulk is given the same doping as the gate region. Thus, a junction of the same kind as the gate-channel junction (except perhaps for the doping concentration values) is already present on the device; thus a JFET is already present. The subsequent diffusion of the gate region into the channel region creates the final, more performant device: it is like having two JFETs with the channel regions connected in parallel. At this point you have to chose if it is worth keeping the two devices separated or not. It turns out that, while it is possible to keep the two devices separated, it is better both from the point of view of performance and feasibility to make them work as one single device. In short the gate and bulk regions are hardwired together in every JFET.

Notes

  • The situation is quite different for small signal (depletion) MOSFETs: for these devices, keeping the bulk and the gate terminals separated is like having a device made of a MOSFET and a JFET with parallel channels, which may be useful in some circumstances. The standard NXP-Philips BSV81 depletion MOSFET is an example of this kind of device.
  • Note also that the above statement is strictly true only for discrete JFET devices. Analog Devices, in some of its high performance OpAmps, uses input JFETs whose bulk terminal is not connected to their gate but goes to a bias network, and this allows an order of magnitude reduction in their gate bias current and better temperature behavior of this parameter (it increases less with the junction temperature compared to standard JFETs).
\$\endgroup\$
6
  • \$\begingroup\$ Thank you, do you agree that your answer contradicts what other people say (at least, this contradict "Justme" who stated, without telling if he means jfet or mosfet, that there are not connected). ? \$\endgroup\$ Aug 5 at 18:04
  • 1
    \$\begingroup\$ @MathieuKrisztian I agree, but I cannot deny what I know from my engineering training. Also, if you look at the JFET image you’ve added to your question, you see immediately the two parallel structures: the bulk (substrate) region has the same depletion effect on the channel that the gate region has. Their hardwiring, when there’s no need of building a thin gate oxide region, is the most natural and useful choice. \$\endgroup\$ Aug 5 at 18:12
  • 1
    \$\begingroup\$ ok thank you. Please note tha tthe schematic is from me : I drawn it by myself as a synthesis of looking at various sources on the web and in books, because none of the schematics that I found were pedagogic enough from my point of view. Your explanation is the best one and you are the only one who understood my question. I give you the accepted answer. Thanks for having shared your knowledge. \$\endgroup\$ Aug 5 at 20:18
  • \$\begingroup\$ @MathieuKrisztian oh, however it is a nice picture. It describes in a simple le but correct way what it really happens. \$\endgroup\$ Aug 5 at 20:21
  • 2
    \$\begingroup\$ @MathieuKrisztian yes, this is true. In ordinary MOSFETs the bulk terminal is connected to the source one of the device at the case level only to avoid the “kink” effect on the \$I_\text{DS}=f(V_\text{DS})\$ characteristic. In small signal enhancement devices, the bulk (B) terminal is mostly made available to the user. \$\endgroup\$ Aug 5 at 20:52
4
\$\begingroup\$

A MOSFET is a 4-terminal device: gate, drain, source, and body. If you buy a discrete MOSFET it is likely that the manufacturer has connected the source to the body, but this is not required.

In your diagram the gate is not connected to the body. There is a thin insulating layer between the gate itself (colored gray) and the body underneath (colored blue).

\$\endgroup\$
3
  • \$\begingroup\$ ok, I agree with your explanation, for the case of the MOSFET, because there is an insulating layer. But what about the case of the JFET ? (there is no insulating layer for JFET) \$\endgroup\$ Aug 5 at 17:36
  • 1
    \$\begingroup\$ I don't think you have shown us what kind of JFET construction you are talking about. If the gate and substrate have an ohmic connection then you don't really have a substrate at all, just a giant gate. If they are touching but junction isolated then I would not say that they are connected at all. \$\endgroup\$ Aug 5 at 18:20
  • \$\begingroup\$ I'm not aware that there are several possible JFET constructions. \$\endgroup\$ Aug 5 at 20:16
3
\$\begingroup\$

There is no hard rule. There are many structures. Connecting the JFET gate to substrate increases the transconductance at the cost of increased gate capacitance. Connecting the substrate to the source reverses this.

On monolithic IC, the substrate is common to all devices. For the common P-type, it's normally connected to the most negative power supply. But for P-channel devices on a P-substrate, you need an "N-well" that serves as a local substrate. For CMOS digital circuits, you usually connect all the N-wells to the most positive supply, but for mixed-signal circuits it's sometimes useful to modulate the gate threshold by adjusting the N-well bias for individual transistors.

And then there are vertical MOSFETS, SOI devices, N substrates, many variations and many ways to connect them...

\$\endgroup\$
2
\$\begingroup\$

No, gate is never connected to substrate.

You need gate and substrate to be isolated to be able to control the gate voltage to turn the transistor on and off.

\$\endgroup\$
4
  • \$\begingroup\$ but in the case of JFET, since there is no insulating layer, isn't it that the gate is connected to the substrate ? \$\endgroup\$ Aug 5 at 17:38
  • 2
    \$\begingroup\$ @MathieuKrisztian How do you actually define connected? Is being separated by a depletion region at a reverse-biased PN junction considered "connected" under your definition or not? \$\endgroup\$
    – nanofarad
    Aug 5 at 18:09
  • \$\begingroup\$ by "connected", I mean no electric resistance, or negligeable electric resistance. So a reverse-biased PN junction is "not connected". \$\endgroup\$ Aug 5 at 20:16
  • \$\begingroup\$ The JFET gate is comparable to a MOSFET gate, even if JFET gate has no insulation. So also JFET gate has extremely high impedance, which is negligible. JFET gate is a reverse biased PN junction, so it does not conduct. Not very well at least. The leakage current is in picoamps range, maybe nanoamps range max. \$\endgroup\$
    – Justme
    Aug 5 at 21:37

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.