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I am looking at the Analog Devices Introduction to SPI Interface and it has this diagram for SPI mode 2...

enter image description here

It shows that the first data bits do not appear on MOSI and MISO until after (1) CS goes low, and then (2) CLK goes low.

In other words, this seems to show that no data is sampled on the first falling edge of CLK after CS goes low.

Is this correct? I thought the first data bits were set up on the falling edge of CS and then sampled on the first falling edge of CS.

Here is another SPI mode 2 diagram from DLNWare that shows the data bits setting up on the falling edge of CS and then being sampled on the first falling edge of CLK thereafter...

enter image description here

It even specifically says "The data must be available before the first clock signal falling".

Which is right? In SPI mode 2 where CLK is idle HIGH and data is sampled on FALLING edge: after a falling CS edge, when is the first data bit read - on the first falling CLK edge or the second? Is it necessary to add an extra L/H/L CLK cycle at the beginning of each CS cycle that does not actually clock any data bits, so that there are n+1 CLK cycles to send n bits?

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    \$\begingroup\$ I think I had the same problem with an PMOD-AD1 circuit that contains an AD7476A. Unless I'm wrong, the first bit appears on the falling edge of CS. \$\endgroup\$
    – Antonio51
    Aug 7, 2021 at 7:39
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    \$\begingroup\$ Page 22 of AD7476A datasheet : CS going low clocks out the first leading zero to be read in by the microcontroller or DSP. The remaining data is then clocked out by subsequent SCLK falling edges beginning with the second leading zero. Thus, the first falling clock edge on the serial clock has the first leading zero provided and also clocks out the second leading zero. For the AD7476A, the final bit in the data transfer is valid on the 16th falling edge, having been clocked out on the previous (15th) falling edge. \$\endgroup\$
    – Antonio51
    Aug 7, 2021 at 7:46
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    \$\begingroup\$ Isn't CPOL=1, CPHA=1 actually "mode 3?" In which case the caption is in any case contradictory. \$\endgroup\$
    – TypeIA
    Aug 7, 2021 at 9:28
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    \$\begingroup\$ SPI modes 0-3 are not standardized. For eg: Microchip n Texas have different definitions for it. \$\endgroup\$
    – Mitu Raj
    Aug 7, 2021 at 10:17
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    \$\begingroup\$ I guess I understand your question. I think this is implementation specific. In Texas SPI, you don't find that extra cycle for (1,1) operation. Slaves drives first data on MISO after CS goes low (or makes the first data ready on MISO even before it) and the first falling edge from master sclk can then sample that data. \$\endgroup\$
    – Mitu Raj
    Aug 7, 2021 at 11:08

2 Answers 2

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I tested this on one of Analog Devices' own AD5766 chips, and the chip most definitely samples the first data bit off the DIN line on the first falling edge of CLK after CS goes low. The master must set up the first data bit on MOSI before the initial falling edge of CLK (probably wise to do it 1/2 clock cycle time before).

The white paper diagram is just wrong and if you follow it then your chips will see everything left shifted by one bit and will not work.

This is a better reference for SPI timings... http://dlnware.com/theory/SPI-Transfer-Modes

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I thought the first data bits were set up on the falling edge of CS and then sampled on the first falling edge of CS.

CS means chip select and no, data is not set up on the CS edges; they are set up on one edge of the clock and read by the slave on the other edge. Data has to be generated on one CLK edge and read on the other.

I think the Analog Devices' white paper diagram is quite badly drawn.

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  • \$\begingroup\$ So in mode 2 where CLK is idle HIGH and data is sampled on FALLING edge: after a falling CS edge, when is the first data bit read - on the first falling CLK edge or the second? \$\endgroup\$
    – bigjosh
    Aug 7, 2021 at 8:37
  • \$\begingroup\$ I'd say the diagrams are just wrong (for an introduction to SPI) - e.g. mode 3 shows exactly the same waveform as mode 2, just with different sampling/shifting markers. That might be a valid SPI communication, but is not what usually happens when switching between the modes. \$\endgroup\$
    – asdfex
    Aug 7, 2021 at 8:44
  • \$\begingroup\$ @bigjosh you have to be clear about data sampling. Are you talking about the master sampling data it wishes to send or, the master wanting to sample data coming from a slave or, the slave sampling incoming data or the slave sampling the internal data it wishes to transmit to the master. \$\endgroup\$
    – Andy aka
    Aug 7, 2021 at 9:05
  • \$\begingroup\$ @Andyaka I don't think it matters for the question, but we can take the easiest case - the slave sampling a data bit being sent by master. Happens on a falling CLK edge. Question is: which falling CLK edge after the falling CS edge for the most significant bit sent by the mater? \$\endgroup\$
    – bigjosh
    Aug 7, 2021 at 9:19
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    \$\begingroup\$ A slave receiving data from a master does not sample on the same CLK edge that the master uses for outputting that data. It cannot happen like this. Master produces data on one edge and the slave receives that data by sampling the other edge. The "other edge" is the only stable place for the slave to sample data @bigjosh \$\endgroup\$
    – Andy aka
    Aug 7, 2021 at 9:25

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