RISC-V PMP limits the physical addresses accessible by software running on a hart (hardware thread).
Source: edX course on Introduction to RISC-V, Chapter 4. Developing RISC-V, The Privileged Specification
(PMP is Physical Memory Protection).
I know what a software thread is, it's a sequence of instructions executed sequentially.
What exactly is a hardware thread in this context?
Additional context (copied and pasted from edX course material):
A common feature of most modern processors is some way of performing secure remote computation or a “trusted execution environment”. Examples of this technology include Intel Software Guard Extensions (SGX), AMD Secure Encrypted Virtualization (SEV), and Arm TrustZone. While the RISC-V ISA does not provide an end-to-end solution for Trusted Execution Environments, the physical memory protection (PMP) capabilities are a solid foundation on which one might construct such a system.
RISC-V PMP limits the physical addresses accessible by software running on a hart (hardware thread). An optional PMP unit provides per-hart machine-mode control registers to allow physical memory access privileges (read, write, execute) to be specified for each physical memory region. The PMP values are checked in parallel with the PMA checks we covered in the last section. The granularity of PMP access control settings are platform-specific and within a platform may vary by physical memory region, but the standard PMP encoding supports regions as small as four bytes