RISC-V PMP limits the physical addresses accessible by software running on a hart (hardware thread).

Source: edX course on Introduction to RISC-V, Chapter 4. Developing RISC-V, The Privileged Specification

(PMP is Physical Memory Protection).

I know what a software thread is, it's a sequence of instructions executed sequentially.

What exactly is a hardware thread in this context?

Additional context (copied and pasted from edX course material):

A common feature of most modern processors is some way of performing secure remote computation or a “trusted execution environment”. Examples of this technology include Intel Software Guard Extensions (SGX), AMD Secure Encrypted Virtualization (SEV), and Arm TrustZone. While the RISC-V ISA does not provide an end-to-end solution for Trusted Execution Environments, the physical memory protection (PMP) capabilities are a solid foundation on which one might construct such a system.

RISC-V PMP limits the physical addresses accessible by software running on a hart (hardware thread). An optional PMP unit provides per-hart machine-mode control registers to allow physical memory access privileges (read, write, execute) to be specified for each physical memory region. The PMP values are checked in parallel with the PMA checks we covered in the last section. The granularity of PMP access control settings are platform-specific and within a platform may vary by physical memory region, but the standard PMP encoding supports regions as small as four bytes

  • \$\begingroup\$ Can you provide an actual link to the source of the quotation? \$\endgroup\$ Aug 7, 2021 at 17:10
  • \$\begingroup\$ @ElliotAlderson you need to login to edX to read it: learning.edx.org/course/… \$\endgroup\$ Aug 7, 2021 at 17:15
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    \$\begingroup\$ A few years ago it was true that CPU clock speeds were so much faster than memory speeds that, even with the fastest caches, you couldn't keep the CPU supplied with instructions and data. Then, a CPU was supplied with 2 (or 4) sets of state (registers, flags etc) and L1 caches to match. The CPU could alternate between two (or 4) different tasks, each with its own state, running fast enough to keep up with the memory supplying each. Intel called this hyperthreading; I expect this is the RISC-V equivalent. \$\endgroup\$
    – user16324
    Aug 7, 2021 at 17:54
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    \$\begingroup\$ @user_1818839 the vendor-neutral term is SMT (simultaneous multithreading). \$\endgroup\$
    – hobbs
    Aug 7, 2021 at 18:11
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    \$\begingroup\$ I would have thought it was a feature of the mounting screw. \$\endgroup\$ Aug 8, 2021 at 18:12

2 Answers 2


The comments already pointed to the right direction. It is easier starting from "what is a core".

From "Volume II: RISC-V Privileged Architectures V1.10":

A RISC-V hardware platform can contain one or more RISC-V-compatible processing cores together with other non-RISC-V-compatible cores, fixed-function accelerators, various physical memory structures, I/O devices, and an interconnect structure to allow the components to communicate. A component is termed a core if it contains an independent instruction fetch unit. A RISC-V-compatible core might support multiple RISC-V-compatible hardware threads, or harts, through multithreading.

From "Volume I: RISC-V User-Level ISA V2.2"

The base RISC-V ISA supports multiple concurrent threads of execution within a single user address space. Each RISC-V hardware thread, or hart, has its own user register state and program counter, and executes an independent sequential instruction stream. The execution environment will define how RISC-V harts are created and managed. RISC-V harts can communicate and synchronize with other harts either via calls to the execution environment, which are documented separately in the specification for each execution environment, or directly via the shared memory system. RISC-V harts can also interact with I/O devices, and indirectly with each other, via loads and stores to portions of the address space assigned to I/O.

We use the term hart to unambiguously and concisely describe a hardware thread as opposed to software-managed thread contexts.

In the base RISC-V ISA, each RISC-V hart observes its own memory operations as if they executed sequentially in program order. RISC-V has a relaxed memory model between harts, requiring an explicit FENCE instruction to guarantee ordering between memory operations from different RISC- V harts.

From the above, the parallel between hart and Intel's Hyper-threading is very good.

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    \$\begingroup\$ From what you've quoted, looks like there may be a parallel. From what I've gathered earlier, Intel implements separate decoding (instruction to the out-of-order reorder buffer [ROB]) and retiring (completed results retired from the ROB back into in-order register results.) But Intel does not implement separate registration stations or added functional units, which take up serious real-estate. So both hyperthreads still compete for pretty much everything else except that. From your quoting, I don't see anything about separate branch prediction. Did you come across something there? Thanks & +1! \$\endgroup\$
    – jonk
    Aug 8, 2021 at 0:20
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    \$\begingroup\$ Brach predictor state needs to be separate. Not sure if the actual hardware needs to be duplicated or not, that's probably more of an implementation detail. \$\endgroup\$ Aug 8, 2021 at 9:01
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    \$\begingroup\$ @jonk Thanks for the comment. The RISC-V documents/standards I know normally don't enforce details regarding the implementation. It is common to see comments regarding design decisions (instruction encoding that allows separate, and parallel, decoding circuits comes to mind) that clearly share a lot of the experience from older RISC architectures. Congress presentations, papers and commercial documentation (e. g. SiFive) are more detailed but I don't recall one that addresses your specific question. \$\endgroup\$
    – devnull
    Aug 9, 2021 at 10:26

A hardware thread is basically a separate execution context - separate, isolated set of registers, page tables, and other microarchitectural state that would otherwise need to be saved/restored during a context switch. Hardware threads look like separate compute cores to the operating system, but they will time-share on the same physical core. The advantage of doing this is that the other hardware thread can take over when the first one stalls the pipeline or similar. Other terms for this functionality are SMT and hyperthreading.

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    \$\begingroup\$ SMT = Simultaneous MultiThreading; hyperthreading = Intel's trademarked implementation of SMT \$\endgroup\$
    – Oskar Skog
    Aug 8, 2021 at 16:57

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