Here is the source code of what I created for experimental purpose:
library ieee;
use ieee.std_logic_1164.all;
entity experiment_5 is
end entity;
architecture beh of experiment_5 is
constant myconstant : integer := -1;
signal mysignal : integer := -3;
function add_1(
a: integer;
b: integer)
return integer
is
begin
return a+b;
end function add;
function add_2(
a: integer;
b: integer)
return integer
is
begin
return a+b+myconstant;
end function add_2;
function add_3(
a: integer;
b: integer)
return integer
is
begin
return a+b+mysignal;
end function add_3;
begin
process
begin
report "result is " & integer'image(add_3(3,7)) severity warning;
report "result is " & integer'image(add_3(10,12)) severity warning;
wait;
end process;
end architecture beh;
Now as expected, the add_1 works just fine and add_3 does not compile. Compiling add_3 gives error message: "# Error: COMP96_0391: experiment_5.vhd : (37, 13): Cannot access "mysignal" from inside pure function "add_3".
"
This is all well and good. My questions are:
- Why does add_2 compile although it accesses something outside the function which is the constant outside it and is not passed to it as a parameter, and add_2 is declared as a pure function!
- Are impure functions supposed to be synthesizable under any circumstances in VHDL?
return a + b - 1;
which is pure. Try a generic : that's a more interesting case because its value isn't known until elaboration (after which, it cannot change) 2) Sure. There are circumstances where they can be. \$\endgroup\$