My understanding of interfacing a standard SRAM chip is the following: When the host wants to write, the OutputEnable# is driven high to bring the SRAM data bus to High-Z and the host is driving the bus. When reading, OutputEnable# is low and the SRAM is driving the bus.
What happens if I accidentially enable the output of the SRAM while driving the outputs on the host side at the same time? Will there be physical damage?
Yes, there may be physical damage. The longer the situation persists, the more the chance for damage. In case this is a problem you foresee happening often in your setup, you should probably work out a better scheme, or at the very least include a series resistor in each of the data lines. The resistor should be chosen such that in the worst case (both sides driving to opposite logic), the current through the resistor should be less than the current drive capability of the IC with the lower current drive capability. Note that in doing so, you will most definitely sacrifice in the speed the data bus is capable of operating at without the series resistance.
What you're describing is called bus contention. I've personally only seen this cause damage once and I was using '80's era technology at the time. Most modern microcontrollers have bus arbitration logic built-in so that this won't happen when they are the only master. But if you have multiple bus masters, this can certainly occur.
The most common symptoms would be glitching or incorrect values alternating with correct values very rapidly. You would easily be able to see this with a logic analyzer. It can be seen with an oscilloscope but I find that it's harder to identify as such.
With a modern microcontroller acting as a single bus master, this will rarely be an issue (assuming you let the micro handle OE# generation and don't force the pin yourself). With multiple bus masters, I usually put a small Programmable Logic Device (PLD) in the system and design a separate bus arbiter to ensure that this does not happen.
