I'm having problems when trying to synchronize output from IR camera and hdmi transmitter. I use cyclone FPGA and ulis IR sensor, for describing how I use Verilog.
Sensor frame rate is 60 fps, same applies for hdmi transmitter. Pixel clock for hdmi is circa 25.03Mhz. Parameters for sensor are fixed and cannot be changed. Output from sensor firstly runs through image pipeline before it is transmitted. I use double buffering - one frame is beeing written to b1 while frame from b2 is beeing transmitted.
The problem is that the frame rate from sensor isn't exactly 60fps, it is little faster. Hdmi transmitter transmits with delay circa 25000ns. Therefore after some time sensor outruns the hdmi transmitter and writes to the same buffer, from which the hdmi transmitter reads the data. This causes that half of new and half of old image is beeing displayed on monitor.
I've tried to use fifo instead buffers, but with this technique after some time I display images with significant delay. I tried to skip some pixels, synchronize writing to buffers, using 2 different clocks for the transmitter (some frames transmitted with faster clock to compensate for the delay), but all those attempts failed.
I'm new in image processing and don't know what to try next. I would greatly appreciate any advice. Thanks in advance.