# How to drive 3 half-bridges using as few pins as possible?

I’m working on a tiny BLDC controller and the microcontroller only has 12 usable pins to begin with so I’m trying to come up with ways to save some. The straightforward way to drive a half-bridge is with a pair of pins, one for the high and one for the low side MOSFET. For a three phase driver that’s six pins, but those pins won’t exhibit the full range of bit patterns. For example, you generally don’t want to see the low and the high side MOSFETs active at the same time.

Sure enough, out of the 2^6 states we only care about 6 while the motor is running and add another one for when it’s stopped. That fits in 3 bits so it should be possible to use 3 pins to switch the MOSFETs, but this is where I’m stuck. Are there already devices that routinely do this? If I wanted to implement this using logic components, how would I go about doing that?

This is the truth table that I'm trying to compress:

Step AH AL BH BL CH CL Note
1 1 0 0 0 0 1
2 1 0 0 1 0 0
3 0 0 0 1 1 0
4 0 1 0 0 1 0
5 0 1 1 0 0 0
6 0 0 1 0 0 1
7 0 0 0 0 0 0 No drive
• Learn what a karnaugh map is. Also use diodes and resistors at the gate to make turn on time slower than turn off time. I would be wary about the synchronization of multiple bit transitions since they won't be perfect. You want to encode states in gray code for sure. But if tiny is the goal then this is misguided. You're going to end up using more much more space than using an MCU with more pins, even if the MCU is a massive 28mm x 28mm QFP with 208pins. Discrete ICs of several $mm^2$ per gate can't compete with VLSI of millions of gates per $mm^2$ Commented Aug 11, 2021 at 2:20
• Are you tring to use a BLDC motor as a stepper motor? why not just use an ESC? Commented Aug 11, 2021 at 2:22
• This sounds like a job for a very small FPGA or (long ago) a PAL.
– user16324
Commented Aug 11, 2021 at 12:51
• @jonk added a table to the question. An FPGA would work great, they just don't make them this small (read, cheap).. Commented Aug 11, 2021 at 23:01
• You probably want your 8th state to be one where all low side switches are closed so that you can either brake or precharge all your bootstrap capacitors from standstill. Commented Aug 12, 2021 at 0:12

If you are willing to consider Gray coding of your IO then:

$$\begin{array}{c|c} \text{States} & \text{Drive Outputs}\\\hline {\begin{smallmatrix}\begin{array}{cccc} IO_2 & IO_1 & IO_0\\\\ 0&0&1\\ 0&1&1\\ 0&1&0\\ 1&1&0\\ 1&1&1\\ 1&0&1\\ x&0&0 \end{array}\end{smallmatrix}} & {\begin{smallmatrix}\begin{array}{cccccc} AH & AL & BH & BL & CH & CL\\\\ 1&0&0&0&0&1\\ 1&0&0&1&0&0\\ 0&0&0&1&1&0\\ 0&1&0&0&1&0\\ 0&1&1&0&0&0\\ 0&0&1&0&0&1\\ 0&0&0&0&0&0\\ \end{array}\end{smallmatrix}} \end{array}$$

Then, if I didn't screw this up, it follows that:

$$\begin{array}{r|l} \text{Drive Output} & \text{Logic}\\\hline {\begin{smallmatrix}\begin{array}{l} AH\vphantom{\overline{IO_2}\:\cdot\: IO_0}\\ AL\vphantom{IO_2\:\cdot\: IO_1}\\ BH\vphantom{IO_2\:\cdot\: IO_0}\\ BL\vphantom{\overline{IO_2}\:\cdot\: IO_1}\\ CH\vphantom{IO_1\:\cdot\: \overline{IO_0}}\\ CL\vphantom{\overline{IO_1}\:\cdot\: IO_0} \end{array}\end{smallmatrix}} & {\begin{smallmatrix}\begin{array}{c} \overline{IO_2}\:\cdot\: IO_0\\ IO_2\:\cdot\: IO_1\\ IO_2\:\cdot\: IO_0\\ \overline{IO_2}\:\cdot\: IO_1\\ IO_1\:\cdot\: \overline{IO_0}\\ \overline{IO_1}\:\cdot\: IO_0 \end{array}\end{smallmatrix}} \end{array}$$

Whether or not this helps, is another question. But it may allow you to get a really cheap PAL (if they still make something like that) or use some simple external logic. It's only six AND gates.

You only need to change one IO pin at a time, too. Which I think improves the idea a bit.

(This question takes me back to 1974, by the way, when I was designing my first CPU out of 7400 logic and struggling with the instruction decoder. Had I not then learned to enjoy these kinds of questions, I'm sure I would have given up and failed.)

• I think that would work. Six AND gates and three inverters using discrete components would be a bit much to save three pins, but like you're saying, put in a single package even the cheapest PAL/FPGA/CPLD could handle this task. Trouble is where I'm ordering my boards from (JLCPCB) it's slim pickings for these components, but I can always add it after. Anyway, I'll come back and mark this as an answer when I have something more to report. Commented Aug 12, 2021 at 5:51
• @Gunchars Cool. Best wishes! And yes, I agree with what you wrote. :) I'm also pleased with the idea of just having to change one pin at a time. This avoids some hypothetical difficulties, as well as perhaps allowing the software to be slightly easier -- maybe.
– jonk
Commented Aug 12, 2021 at 6:05
• @Gunchars Any good news yet?
– jonk
Commented Aug 24, 2021 at 3:58
• I'm afraid not. Still working on the boards, but I think I'll use the 6 pins and add an IO expander if I need it. I couldn't find any programmable logic devices that didn't cost more than the rest of the board and I can't justify using discrete components. The potential for timing issues like shoot through was a concern too. That said, your answer is still great and thank you for taking the time to work through this with me. Commented Aug 24, 2021 at 4:48
• @Gunchars Interesting results. Thanks for the update. That's the kind of balancing I've done in the past, too. So it all makes sense. Best wishes on your project!
– jonk
Commented Aug 24, 2021 at 5:16