So the context is about DDR memory, which is a type of DRAM memory.
DRAM memories typically contain a lot of memory which is internally organized into a 2D array with rows and columns anyway, so to conserve the amount of address pins, there is only a single set of address pins, that are uses for sending both the row and column addresses one after another.
So let's say it's the 1970s and you have a 64 kilobit memory chip. It would require 16 address pins just for the address pins alone. So if the 16 address bits are sent in two phases, first the 8 bit row address and then the 8 bit column address, there is only need for 8 address pins. So the whole memory chip can now be packaged into a cheaper package with a total of 16 pins instead of more expensive 24 pin package.
And thus we still have dynamic memories with row and column addresses.