I'm looking to use a P-channel high-side MOSFET to enable/disable some sensors and peripherals connected to an ESP32. The peripherals use 3.3V and the ESP32 runs on a 3.3V logic level.

I'm not an electrical engineer, and I'm probably a bit out of depth on selection of the parts in this schematic. I could see a few different circuits to enable me to use a P-Channel MOSFET. Some circuits use a general-purpose NPN transistor to pull down the MOSFET gate to ground when signal is applied to the base of the transistor, while other circuits directly connect the MCU GPIO pin to the MOSFET gate.

Could someone help me understand when this transistor is needed, and if the transistor will be needed for this particular case (3.3V MCU, turning on/off a 3.3V supply using an AO3401A MOSFET. An alternative part number available easily is SI2301DS. I'm unfortunately constrained to these 2 part numbers because JLCPCB use these in their basic parts library.

Edit: I have added a few jumpers (JP6/JP8) to be able to bypass the MOSFET and transistor, should the need arise. The peripherals consume upto 200mA current based on the max current consumption as specified in the datasheets. The "average" consumption is under 50mA. I'm unusure if this matters, since the specific part numbers seem to support current in a low single digit Ampere.


schematic with p-channel mosfet on high side

  • 1
    \$\begingroup\$ 100 k pull-up, is that fast enough for your application? If yes, what's the Vgsth of Q2? \$\endgroup\$
    – winny
    Aug 12, 2021 at 13:44
  • \$\begingroup\$ I'm not looking for fast switching. Will probably be switching on and off a few times an hour. Vgs(th) for Q2 (AO3401A) is between -0.5V to -1.3V. \$\endgroup\$ Aug 12, 2021 at 17:30
  • \$\begingroup\$ That helps, but there could still be reasons not to go too slow, SOAR or your load requiring it. If not, then you’re good. \$\endgroup\$
    – winny
    Aug 12, 2021 at 17:45
  • \$\begingroup\$ You don't need the transistor. You do need to consider what will happen when the FET switches on. You say that your load 'only' draws up to 200mA, but what about surge current? If it is too much for your power supply it may glitch or reset the ESP32. So, which 'sensors and peripherals' are you powering, and what are you powering the system from? \$\endgroup\$ Aug 12, 2021 at 23:18
  • \$\begingroup\$ @BruceAbbott: The power supply on the ESP32 is an SY8008B which is capable of providing upto 1A current. The peripherals consist of: 1. a GPS module (rated at 100mA max, 25mA typical) 2. MS5611 baro (1.4mA peak) 3. MPU9250 (10mA peak) 4. a couple of LEDs (30mA) \$\endgroup\$ Aug 13, 2021 at 4:55

2 Answers 2


The transistor is needed when the source voltage of the P-channel MOSFET is higher than the logic level you are using to control it.

To turn a P-channel MOSFET off the gate has to be driven up to a voltage near that of the power supply. That is what the 100kΩ resistor R8 does in your schematic. It's then turned on by pulling that gate down below that threshold voltage.

If you're controlling, say, a 12V device and using a 3.3V logic you can't drive the gate up to 12V since your HIGH is only 3.3V. So the transistor is added to act as a switch that can be driven with just 3.3V to turn it on.

Since you are powering 3.3V devices and have a 3.3V logic level the NPN (or N-channel MOSFET as I prefer) is not really needed. Just know that HIGH is off and LOW is on.

Incidentally the NPN can often be replaced with a GPIO pin in Open Drain mode (if the MCU supports it).

  • \$\begingroup\$ If I understand this right, the transistor Q3 (BC847) is not needed since the MCU logic level is same as the source voltage of Q2 (AO3401A). Removing Q3 will cause the logic input to be inverted – sending a high on PWR_EN will cause the MOSFET to turn off, and sending a low on PWR_EN will cause the MOSFET to turn on. \$\endgroup\$ Aug 12, 2021 at 17:38
  • \$\begingroup\$ @KetanPadegaonkar that is correct. \$\endgroup\$
    – Majenko
    Aug 12, 2021 at 17:42

I can't speak to your specific application, but I know a BiCMOS circuit when I see it

I used to design these things. This one is simple and relies on the permissibility of Q2 leaking just a hair. Here's what's happening.

Q2 is HUGE. According to its datasheet, it has an input capacitance of 645 pF. To switch it quickly you need to dump charge out of that cap as fast as possible — and the whole situation is made worse through the use of a simple resistive pull-up resistor. This means you're draining that current (V=IR so I= 33uA) and the charge on Q2's input. That's why the NPN transistor is used. It's the fastest way to drain that current possible.

Side note: that NPN will only drain the node down to Vbe or ~0.5v. In a full-logic world you would need to completely drain the node to 0v. In that case, a BiCMOS design would include an NMOS device parallel with the NPN transistor with an Rds<100K. It would be too small to quickly switch Q2, but it would pull the node to (or near to) zero.

The use of the pull-up resistor R8 suggests that the application doesn't care how fast the PMOS shuts off, but cares an awful lot about how fast it turns on. That might not actually matter, though. This appears to be nothing more than a light switch: a circuit that powers on and powers off something else.

  • 2
    \$\begingroup\$ Actually I wouldn't say this was BiMOS. Sure, it looks like BiMOS and contains a BJT and a MOSFET but BiMOS chooses those components specifically for their characteristics. This is more a RTL inverter controlling half of a CMOS push-pull output stage. The choice of BJT or MOSFET is largely irrelevant, and switching speed is of little consequence. \$\endgroup\$
    – Majenko
    Aug 13, 2021 at 10:46
  • \$\begingroup\$ @Majenko Maybe. It takes a large FET to discharge a large cap. It's the reason BiCMOS exists. The circuit wouldn't use a BJT with the disadvantage of the Vbe drop if the switching speed was irrelevant. And I think the hint here is the 3.3V to 3.3V passage through the FET. Light switch. My guess is that they wanted a slow turn-off cycle (R8) to debounce and provide a predictable transition, but a snap-on because people tend to be impatient. Otherwise they could have slapped a small CMOS inverter and saved the Vbe consequence. \$\endgroup\$
    – JBH
    Aug 13, 2021 at 16:19
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    \$\begingroup\$ Most times I see an NPN it's there purely because it's what is there. If that makes sense. The circuit designer doesn't know any better, and it's the default device they have seen around on the net. And the 100kΩ will be to reduce quiescent current while the NPN is on. The purpose of the circuit is for power saving, after all. \$\endgroup\$
    – Majenko
    Aug 13, 2021 at 17:29
  • \$\begingroup\$ @Majenko Ah. I see your point. I've no experience with bipolar-FET circuit design outside of BiCMOS, and I was designing chips where the processes are restrictive, so the idea that someone could simply slap an NPN in place didn't make sense to me. I see your point with a design like this where the components are discrete. Yeah, the designer may have had nothing else and it happened to work. \$\endgroup\$
    – JBH
    Aug 13, 2021 at 23:02

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