# How can I match a transmission line impedance on the source side?

Suppose that I want to transmit a signal by a coaxial cable to a high-impedance load.

The signal is a single-ended TTL (3.3V) single square impulse from an FPGA output. The package of the FPGA is LQFP-144. The coaxial cable is a 50-ohm RG-174. The load is a high impedance input of an IC like an FPGA/MCU or an oscilloscope input with a 1Mohm internal load.

Also suppose that the FPGA output impedance is less than 50ohm. I have learned it from an IBIS model. Therefore in theory I can match an impedance with one series resistor on the source side.

But the 50-ohm line width on a 0.4mm FR4 is 0.73mm, and the pitch of the LQFP-144 is 0.5mm.

So, my impulse will run towards the load. Then it will reflect off and run to the 50-ohm connector on PCB, then it will reflect off from the connection of PCB line and 50-ohm connector despite any of my impedance matching actions.

Can I match a transmission line impedance on the source side in this case?

• What is the width of the pulse and what frequency? Commented Aug 12, 2021 at 16:05
• @KevinWhite, the rise and fall times of the returning pulse are likely more important in this scenario. Commented Aug 12, 2021 at 16:08

So, my impulse will run towards the load. Then it will reflect off and run to the 50-ohm connector on PCB, then it will reflect off from the connection of PCB line and 50-ohm connector despite any of my impedance matching actions.

Assuming the trace on the PCB is short compared to the rise-time (or fall-time) of the pulse, then very soon after the reflection between the connector and PCB line is generated, another reflection will be generated between the PCB line and the termination resistor you added at the source.

This second reflection will be (very nearly) equal and opposite the first reflection, so the total reflection onto the coaxial cable will be very small.

If this reflection is not acceptable, then you should re-design your PCB stack-up to allow you to make your PCB line $$\Z_0\$$ 50 ohms with a practical geometry.

If you can't put parallel termination of the signal at the receiver side, then you can use source-series termination to match the impedance at the source side.

Also suppose that the FPGA output impedance is less than 50ohm. I have learned it from an IBIS model. Therefore in theory I can match an impedance with one series resistor on the source side.

You are correct. If the driver has output impedance Z_driver and the transmission line has output impedand Z_line, then add series termination Z_term = Z_line - Z_driver. The series termination resistor should be placed as close to the source as possible.

But the 50-ohm line width on a 0.4mm FR4 is 0.73mm, and the pitch of the LQFP-144 is 0.5mm.

This is only true for a specific layer spacing and dielectric constant. Its possible to purchase PCBs with different dielectric constants, or adjust the spacing between layers to get what you want. Typically narrowing the traces or increasing layers spacing will increase impedance, and widening traces or decreasing layer spacing will decrease impedance.

For example, 1oz, 10 mil traces, with 6 mil to the ground plane, and Er=4.7 gives 49.7 ohms impedance on a microstrip impedance calculator and will fit in a 0.5mm pitch. There are a lot of manufacturers, including inexpensive ones, that can make something similar.

But also keep in mind that with the traces so close together you are likely to get cross talk. So its better to just spread them apart anyways if you can. Typically you would want the trace to trace separation to be several times the trace to ground-plane separation.

So, my impulse will run towards the load. Then it will reflect off and run to the 50-ohm connector on PCB, then it will reflect off from the connection of PCB line and 50-ohm connector despite any of my impedance matching actions.

Having the wrong impedance for a very short run is typically OK. So if the distance to the connector is very short then it should be fine to just run the traces at 0.5mm pitch to the connector (except for the issue of cross talk mentioned above). If its not very short then you should use whatever method you can to spread out the traces as soon as possible, and run them at 50 ohms for as much of the distance as you can.

It should be noted that if you are going to add series termination resistors you will probably have to spread out the signals anyways. Even an 0402 size SMD resistor is about 0.5mm wide, and there needs to be clearance between them and the adjacent traces. The only way you could keep the traces at 0.5mm center to center with termination would be to go to really tiny resistors like 0201 or use use some of the multi-resistor packages that are designed for termination.

"Therefore in theory I can match an impedance with one series resistor on the source side.Can I match a transmission line impedance on the source side in this case?"
However you match the impedance on source side, it does not solve the problem as a "termination". It 'may' solve the problem only as a "LPF".
Thus, for your question, you need to match the impedance at the destination by whatever means, match to the coax cable you are using.
Since you have rather short distance from the socket to the receiver device (though it depends on the frequency, thus the characteristics of the pulse), and high impedance on the receiver, you may terminate -parallel termination- right at the coax cable receptacle of the receiver. In this case, you do not need to "terminate" the source side at all.

I hope it is okay resurrecting an old thread, to add a caveat.

Protection diodes to a really well decoupled power supply, which likely is the case in the FPGA input scenario described, will do a better job of clipping the ringing and will reduce effects caused by lack of input termination. (My assumption here is that you specify this because you have no control over the Rx end, otherwise you could have improved that through termination)