I am using a MAX14830 SPI-UART bridge. I am trying to initialize the chip and get it to transmit a few bytes out of one of its UART. I can write to the UART's THR register, which gets added to the TxFIFO of the UART, but the TxFIFO Level keeps increasing. My issue is exactly the same as the one mentioned in this thread. I have checked the ClkDisabl bit as OP mentioned in his answer and the bit is not set.

My initialization procedure for the chip:

  1. Reset chip by setting RST bit in MODE2 register and then clearing it
  2. Set the baud rate to 115200 by setting clock divider to 2 (DIVLSB = 2, DIVMSB = 0)
  3. Set line control register LCR to 3 (8 data bits + 1 stop bit)
  4. Set TrnscvCtrl bit in MODE1 register
  5. Clear FIFOs by setting FIFORst bit in the MODE2 register and then clearing it

After this initialization procedure, I write 3 bytes ('A', 'B', and 'C') to the THR registers, when I check the TxFIFOLvl register I see a 3. Every subsequent write just adds to the FIFO and nothing ever goes out the FIFO and I see nothing on the TX line with an oscilloscope. The TxFIFOLvl register returns to 0 only after I clear the FIFOs again or reset the chip.

Any advice on how I can go about debugging the issue or what areas I should look at? Any help would be appreciated! Here's the datasheet for the MAX14830.

EDIT: I tried outputting the UART clock on one of the GPIO pins on the MAX14830 using the ClkToGPIO bit in the TxSynch register, the clock is always high and doesn't seem to be ticking at all. Here's a picture of the voltage across my crystal oscillator. Crystal part number E1SFA12-3.6864M TR. Looks like the peak to peak voltage is about 100mV and the time period is 1us. Does this mean my crystal isn't functioning correctly?

crystal oscilloscope

EDIT: Adding my code and logs.

#define IRQ_EN 0x01
#define ISR_REG 0x02
#define MODE1 0x09
#define MODE2 0x0A
#define FLOW_LVL 0x0F
#define LCR_REG 0x0B
#define FIFO_TRIG 0x10
#define TX_FIFO_LVL 0x11
#define RX_FIFO_LVL 0x12
#define FLOW_CTL 0x13
#define BRG_CFG 0x1B
#define DIV_LSB 0x1C
#define DIV_MSB 0x1D
#define CLK_SRC 0x1E

void action() {
    Particle.publish("Selecting UART1", "Success");
    Log.info("Selecting UART1");
    Particle.publish("Resetting UART1", "Success");
    Log.info("Resetting UART1");
    SPI_writeRegister(MODE2, 1);
    SPI_writeRegister(MODE2, 0);
    Particle.publish("Setting UART1 baud rate to 115200", "Success"); //clock 3.6864MHz
    Log.info("Setting UART1 baud rate to 115200");
    SPI_writeRegister(DIV_MSB, 0);
    SPI_writeRegister(DIV_LSB, 2);
    //Set 8 bits data + 1 stop bit
    SPI_writeRegister(LCR_REG, 3);
    //set MODE1 TrnscvCtrl bit 
    SPI_writeRegister(MODE1, 16);
    Particle.publish("Resetting FIFOs UART1", "Success");
    Log.info("Resetting FIFOs UART1");
    SPI_writeRegister(MODE2, 2);
    SPI_writeRegister(MODE2, 0);
    //Clear ISR register by reading from it
    Particle.publish("Writing to UART1", "Success");
    Log.info("Writing to UART1");
    Particle.publish("UART1 TX_FIFO_LVL before write = ", String::format("%d", SPI_readRegister(TX_FIFO_LVL)));
    Particle.publish("UART1 TX_FIFO_LVL 1s after write = ", String::format("%d", SPI_readRegister(TX_FIFO_LVL)));
    Particle.publish("Selecting UART0", "Success");
    Log.info("Selecting UART0");
    Particle.publish("UART0 TX_FIFO_LVL after write = ", String::format("%d", SPI_readRegister(TX_FIFO_LVL)));


  • \$\begingroup\$ So what is your clock config then? Crystal? Clock signal? What frequency? Do you use PLL? What multiplier? \$\endgroup\$
    – Justme
    Aug 13, 2021 at 18:17
  • \$\begingroup\$ I am using a 3.6864MHz external crystal oscillator, internal PLL and pre-divider is bypassed by setting PLLBypass bit in CLKSource register. Clock divider is set to 2 [Divider = Clock freq / (16 * baud rate)] and my baud rate is 115200. \$\endgroup\$
    – Harid444
    Aug 13, 2021 at 18:33
  • \$\begingroup\$ Is RTS active and looped somehow with CTS! \$\endgroup\$ Aug 13, 2021 at 22:03
  • \$\begingroup\$ @TonyStewartEE75 Just checked that, CTS is not looped to RTS. CTS is low and RTS is high. \$\endgroup\$
    – Harid444
    Aug 14, 2021 at 4:44

1 Answer 1


From reading the manual it looks like CLKSource register and thus the crystal enable bit, CrystalEn, can only be set by addressing UART0.

You appear to be addressing UART1. Set the bits through UART0 then revert to your desired communication channel.

  • \$\begingroup\$ Thanks! That did the trick! \$\endgroup\$
    – Harid444
    Aug 17, 2021 at 5:40

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