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Inside ISE timing constraint editor window, which following sub-section shall I use set_clock_group to solve the STA setup timing violation path #1 due to cross-clock signal ?

timing_constraint_editor

violation_path

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    \$\begingroup\$ I think you should ask tool specific questions in Xilinx Forum. But since this is ISE which is too old, I doubt if you get any support at all. \$\endgroup\$
    – Mitu Raj
    Commented Aug 16, 2021 at 7:47

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Two comments.

  1. It may be time to consider upgrading to Vivado. ISE is nearing its end of life for the Xilinx FPGA families

  2. When you have a defined clock boundary crossing a common way to flag that in SDC is to use the set_false_path constraint between the two domains. You would only do this if you knew that the crossing was dealt with properly, such as with a FIFO.

Since you're working with a DDR controller, the assumption is that:

  • Inputs use a FIFO re-timed using a DLL with incoming DQS signal
  • Outputs a FIFO and per-lane clock phasing to compensate DDR fly-by timing

In either case, each lane set is its own clock domain, distinct from the reference clock.

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  • \$\begingroup\$ Synchronizing Fast Signals Into Slow Clock Domain might be the more difficult case as described in verilogpro.com/clock-domain-crossing-part-1. I do not understand what you meant re-timed using a DLL as well as clock phasing ? \$\endgroup\$
    – kevin998x
    Commented Aug 18, 2021 at 7:11
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    \$\begingroup\$ DDR3 supports variable DQ/DQS timing that allows the clock/control group to be routed using a ‘fly-by’ topology. The controller compensates the timing for each lane. \$\endgroup\$ Commented Aug 18, 2021 at 14:46
  • \$\begingroup\$ I am still confused as in how does DLL fits into the picture in this case ? \$\endgroup\$
    – kevin998x
    Commented Aug 20, 2021 at 4:05
  • \$\begingroup\$ The read DQS signal is phase-aligned with DQ. To sample the DQ properly, the host must make a 90-degree phase shifted clock. The DLL references DQS and makes this phase-shifted clock. \$\endgroup\$ Commented Aug 20, 2021 at 6:41

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