# Active Clamp Forward Questions

I have some questions on TI active clamp forward, Here are my questions:

1. On pages 4 and 5, the document describes if the output voltage is high enough, the MOSFET on the secondary side, the energy being driven from secondary to primary. I do not know why?

2. Why is the output voltage high enough, will make Q3 and Q5 turn on, does the MOSFET turn on, which depends on the gate voltage?

3. Why the transformer change polarity will make Q3 and Q5 turn off?

Can someone give me some advice?

The structure that is represented is a so-called active-clamped forward (ACF) with self-driven synchronous rectifiers. It means that MOSFETs drive is controlled by the voltage available from the secondary side of the transformer. That voltage depends on three parameters: the input voltage $$\V_{in}\$$, the transformer turns ratio $$\N\$$ and the clamp voltage $$\V_{clp}\$$.

When the primary main N-channel switch turns on, the voltage at the secondary is simply $$\NV_{in}\$$. If the example I give below, considering a 36-V input and a 1:0.166 turns ratio, the drive voltage applied at the forward synchronous rectifier is around 6 V if we neglect the drop in the primary side. If the input now increases to 72 V as in a telecom application, the drive voltage increases to around 12 V. A logic-level MOSFET is thus necessary to ensure a good turn-on at the lowest input and no specific regulator is needed for the upper input range.

When the N-channel turns off, the voltage across the primary side transformer reverses and becomes clamped at the voltage across the clamp capacitor. In my example, it is 58 V at a 36-V input and drops to 32 V at a 72-V input. That new polarity now forward biases the freewheel synchronous rectifier to 9.6 V (36 V) and 5.3 V (72 V). Because of the dependency of these voltages on the input line and clamp level, precautions must be taken to ensure that a) enough drive voltage is always present to bias the MOSFETs and b) a clamp circuit limits the excursion on the gate-source terminals to avoid breaking the transistors. Very often, an additional regulator is associated to the sync rects as in the TI example.

You can use one of the 60+ SIMPLIS templates that I have posted on my webpage and freely simulate one of the active clamped examples as the one below to which I added a pair of synchronous switches:

The simulation time is flashing and shows the typical waveforms for this 3.3-V/30-A ACF converter:

Self-driven synchronous rectification can be tricky especially if pre-bias protection is required. In this case, it is easier to resort to a dedicated secondary-side controller which controls the timing accordingly and safely clamps the $$\V_{GS}\$$ of the individual transistors.

I have covered the small-signal analysis of the ACF in a 3-part series of articles published in the on-line newsletter How2Power.

• Hi Verbal Your explanation is very clear. it seems like the MOSFET on the secondary turn-on is based on the input voltage and the turn ratio. but in the TI document, why can say the output voltage increased will make the MOSFET turn-on (Q3 and Q5)?
– EEC
Aug 17, 2021 at 14:55
• As TI document said, if do not do any protection when the output voltage becomes higher, it will cause a large voltage spike on the Q3 and Q5. do you have any idea? because I do not understand why it will cause a spike.
– EEC
Aug 17, 2021 at 15:09
• I would assume it is linked to the absence of soft recovery for the MOSFET body diodes. As you operate the converter in heavy CCM mode, you may have either a bit of cross-conduction between the two output MOSFETs or, even if there is some deadtime, the hard turn-off of the body diode of the freewheel MOSFET may generate a spike depending on the parasitics. This is the plague of sync rect and MOSFETs should be carefully selected not only based on $r_{DS(on)}$ performance but also on diode $Q_{rr}$ which must be minimized. You can see the snubbers they have installed across the MOSFETs. Aug 17, 2021 at 15:15
• I understand. Thanks.
– EEC
Aug 18, 2021 at 15:01

1.) On pages 4 and 5, the document describes if the output voltage is high enough, to turn on the the MOSFET on the secondary side, the energy being driven from secondary to primary. I do not know why?

A missing part in the Fig 2-2: To MOSFETs turn on Q3 & Q5 gates are biased and referenced to internal ground of the secondary side. When the voltage increases, the Vsource develops against the reference (not shown either). Eventually the voltage on the FET source will reach -Vgs + bias. Once Q5 turns on, current flows through the secondary of the transformer and induce current to the primary as the same way the primary does to the secondary.

2.) Why is the output voltage high enough, will make Q3 and Q5 turn on, does the MOSFET turn on, which depends on the gate voltage?

Explained up there. The picture is not showing the circuitry on FET gates.

3.) why the transformer change polarity will make Q3 and Q5 turn off?

Q5 turn-on mechanism is obvious, Q5 Vgs gets positively biased. (ask if not understanding).
Q3 turns off since the current loop is established through Secondary <-> Q5 <-> Q3 body diode <-> Secondary. That biases Q3 (a certain degree) Vgs negative.

Edit

Why the MOSFET Q3 and Q5 will turn on. The voltage on the gate should be above the source and then the MOSFET witll turn on. But, why the output voltage increase will make MOSFET turn on?

In the schematics drawing, the gate of Q8 (TP17) and the gate of Q6 (TP15) are on the (almost) 12V regulator output: "D18, R29,and Q5" is 12V regulator. "R31, Q7, and D17" is 12V regulator.
While the "output (TP14-TP23) + voltage across L8" (TP16-TP23) is low, the regulators are inactive, and output is below Vgs threshold (analysis why). When the output voltage becomes sufficiently high, thus TP16-TP23 is high, then regulators become active and supplies 12V to Q7 and Q8 gate. So, the FETs turns on.

The third answer, could you explain more?

The statement is explaining Figure 2-3, just under the figure. It is not "Q3 & Q5 turn on", but, "turn on Q5 and turn off Q3" when the transformer changes polarity. Looking at the figure 2-3, Q5 is positively biased by the voltage on secondary (look at the red + & - signs) and the regulator on Q5 gate (of figure 2-3, or Q8 of the schematics) is active, supplying 12V. Thus Q5 turns on.
Meantime, since the secondary is the voltage source (again, look at the fig 2-3), the source of Q3 is more positive(+) than drain(-), reversed biased, and turns off Q3.

• Hi jay 1.) I still do not understand why the MOSFET Q3 and Q5 will turn on, I mean the voltage on the gate should be above the source and the MOSFET witll turn on, but why the output voltage increase will make MOSFET turn on? could you draw a figure let me to easy to understand? 2.) According to the third answer, could you explain more detail, I still confused about it.
– EEC
Aug 17, 2021 at 0:16
• I upload the schematic m could you use this one to let me understand?
– EEC
Aug 17, 2021 at 0:21
• @EEC I will explain it up in the answer.
– jay
Aug 17, 2021 at 2:21
• Thanks, because the document makes me very confused.
– EEC
Aug 17, 2021 at 2:42
• Hi jay, in your explanation, I think there is a mistake.While the "output (TP14-TP23) + voltage across L8" (TP16-TP23) is low, the regulators are inactive. I think the voltage across L8 is TP16-TP14 also equal TP16-Vo.
– EEC
Aug 17, 2021 at 15:03