From https://www.electronics-tutorials.ws/logic/logic_5.html

I learned that Boolean Expression for a 3-input Logic NAND Gate is enter image description here

, and is read as "A AND B AND C gives NOT Q".

I am wondering why it's not read as "NOT (A AND B AND C) gives Q" as this seems to me aligns with the Boolean Expression more.

  • \$\begingroup\$ These two wordings are equivalent. \$\endgroup\$
    – Eugene Sh.
    Aug 17, 2021 at 20:15
  • \$\begingroup\$ Look at Polish notation on Wikipedia. I do not mean yours is Polish notation. But, there are many ways people speak for the same matter. \$\endgroup\$
    – jay
    Aug 17, 2021 at 20:26
  • \$\begingroup\$ Well, we can't have a say on author's matter of choice. \$\endgroup\$
    – Mitu Raj
    Aug 17, 2021 at 20:43
  • 1
    \$\begingroup\$ Or MAYBE because -- Suppose you are designing this function in a CMOS logic, Q' makes more sense. \$\endgroup\$
    – Mitu Raj
    Aug 17, 2021 at 20:53

3 Answers 3


Exciting, what a day! That is the most precise statement. I got the answer from the. posted link!

enter image description here

"Read as" => Read the Symbol from the left to the right: [A & B & C] [gives (the container/function with '&' operation)] [NOT (the hollow dot)] [Q] !!

  1. "NOT (A AND B AND C) gives Q" can be perceived as "Not (A & B & C) but something else may give Q", and that isn't a binary opinion.
  2. Considering the nuance of 1) feels something off, "A AND B AND C gives NOT Q" sounds like "(A & B & C) gives something (and that is) NOT Q". Better!
  • \$\begingroup\$ Hi! I have trouble understanding what you mean by "[gives (the container/function with '&' operation)]" and "[NOT (the hollow dot)]". Would you mind explaining this? Also, why isn't "Not (A & B & C) but something else may give Q" a binary opinion? This seems binary to me as I interpret it saying that since (A & B & C) doesn't give Q, the opposite of it, NOT(A & B & C) is what gives Q. Any explanations would be appreciated! \$\endgroup\$
    – Alexia.
    Aug 19, 2021 at 18:38
  • \$\begingroup\$ @Cheryl, Thanks for accepting my answer. Meantime I am terribly sorry that my answer wasn't good enough. I will try to explain, but cannot promise to be enough. "[gives]" is an action, which is performed by a "function", which does the '&' operations, which is drawn as a "container", which is a shape of box with round on a side. continue.. \$\endgroup\$
    – jay
    Aug 19, 2021 at 18:55
  • \$\begingroup\$ A meant a "binary opinion" by an answer giving either 1 or 0. That is equivalent to " yes or no", but not "doesn't give Q", which can be taken as "may" (uncertain) give "X (don't care)" or /Q. "Don't care" is not considered as a binary answer. \$\endgroup\$
    – jay
    Aug 19, 2021 at 19:02
  • \$\begingroup\$ The other hand, (I thought too, that I did not explain enough), wonder if "(A & B & C) gives (/Q)" is more acceptable instead of "(A & B & C) gives something (and that is) NOT Q". I wanted describe there is an action of "gives/outputs" and the whole word, "NOT Q", is an objective noun . \$\endgroup\$
    – jay
    Aug 19, 2021 at 19:10

It is usually read as your suggestion. But there's no contradiction, both statements mean the same. Why the authors of the site you're referring to chose their way of expressing it - no idea.


Boolean logic's overbar notation isn't very friendly to text editors. The electronics-tutorials.ws folks seem to struggle a bit with this.

Here at SE, we can deal. The expression, formally, would be:

$$ Q = \overline{ABC} $$

Anyway, I used an SE syntax called mathjax to show this fancy overbar stuff, which codes as follows:

Q = \overline{ABC}

More about this here: Most common MathJax uses in Electrical Engineering?

Now, if you were to code this as a C language expression (C being a language that doesn't know anything about overbars) you'd get:

 Q = !(A && B && C);

They're nevertheless the same expression. As there are so many people who use C, you'll see this form often as it's easier to represent with normal text. Verilog borrows from C and uses this form as well. VHDL? Enjoy your verbose typing...

Anyway, all these forms read as "NOT (A AND B AND C) gives Q", as you said.

Now, to say "(A AND B AND C) gives NOT Q" is a bit confusing, but it's still valid, kind of. Nevertheless, C language and Verilog will not allow a unary NOT operator on the left-hand side of an expression.

That is, this format isn't allowed:

  !Q = A && B && C;    // "(A AND B AND C) gives NOT Q" - nope

While this format is a-ok:

   Q = !(A && B && C);  // "NOT (A AND B AND C) gives Q" - ok

Bottom line: your reading as "NOT (A AND B AND C) gives Q" is preferred to the one given on that website.


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