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I am working on SPI master and slave blocks.
In the design, SPI slave has only input signals ( CLK, cs(chip select) and MOSI), SPI master has only output signals ( CLK, cs(chip select) and MOSI).
I have done with a design SPI slave in VHDL and started to work on the SPI master.
Could someone explain the difference between a simulation a slave and a master in VHDL?
A typical spi master has 3 outputs (CLK, CS, MOSI) and one input (MISO). The SPI master drives the clock, and clocks data out and in.
A spi slave has 3 inputs (CLK, CS, MOSI) and one output (MISO), sometimes it has registers that can be selected to clock data out.
Your design would look like this:
Master - 3 outputs (CLK, CS, MOSI). Slave - 3 inputs(CLK, CS, MOSI).
The master will need to drive the clock and assert the CS line (usually it goes low) when data is on the bus. In many designs the master will take the system clock and use a counter to divide the clock to a slower frequency. Sometimes a parallel to serial shift register is used with an enable to clock out the data to the MOSI line.
