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I am working on SPI master and slave blocks.

In the design, SPI slave has only input signals ( CLK, cs(chip select) and MOSI), SPI master has only output signals ( CLK, cs(chip select) and MOSI).

I have done with a design SPI slave in VHDL and started to work on the SPI master.

Could someone explain the difference between a simulation a slave and a master in VHDL?

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    \$\begingroup\$ Master drives the clock. Otherwise the same I think. Are you forgetting MISO? \$\endgroup\$
    – DKNguyen
    Aug 18, 2021 at 14:05
  • \$\begingroup\$ One possible example, master is expected to support all spi mode combinations, a slave can be simplified to support only one phase and polarization and is not typically configurable in the field. \$\endgroup\$
    – crasic
    Aug 18, 2021 at 15:56
  • \$\begingroup\$ @DKNguyen in the proposed design I don't need MISO signal. it will be a design a slave device. So...I have slave receive SPI and transmit SPI master. The first one has only inputs and the second one has only outputs. \$\endgroup\$
    – Franki Lee
    Aug 19, 2021 at 6:03

1 Answer 1

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A typical spi master has 3 outputs (CLK, CS, MOSI) and one input (MISO). The SPI master drives the clock, and clocks data out and in.

A spi slave has 3 inputs (CLK, CS, MOSI) and one output (MISO), sometimes it has registers that can be selected to clock data out.

Your design would look like this:

Master - 3 outputs (CLK, CS, MOSI). Slave - 3 inputs(CLK, CS, MOSI).

The master will need to drive the clock and assert the CS line (usually it goes low) when data is on the bus. In many designs the master will take the system clock and use a counter to divide the clock to a slower frequency. Sometimes a parallel to serial shift register is used with an enable to clock out the data to the MOSI line.

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  • \$\begingroup\$ Hello! Thank you for your reply! Do you have an example of a realisation of SPI master? Could you please share ? I have found examples, but all of them works as a state machine. \$\endgroup\$
    – Franki Lee
    Aug 19, 2021 at 6:06
  • \$\begingroup\$ honestly, it difficult to understand how block without inputs work. I create internal signals for clk and cs, but what I have to do with mosi I have no idea \$\endgroup\$
    – Franki Lee
    Aug 19, 2021 at 8:04

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