I am working on SPI master and slave blocks.
In the design, SPI slave has only input signals ( CLK, cs(chip select) and MOSI), SPI master has only output signals ( CLK, cs(chip select) and MOSI).
I have done with a design SPI slave in VHDL and started to work on the SPI master.
Could someone explain the difference between a simulation a slave and a master in VHDL?