Case and nested case statements in Verilog

This is the always block of the RTL having nested case statements inside:

always@(posedge clk)
begin
state<=in;
//index<=3'b000;

if(rst)
begin
state<=3'bxxx;
out<=3'bxxx;
end
else
case(state)
s0:  begin
index<=3'b000;
case(index)
3'b000:begin
if(ram && !visited[0])
begin
state<=s0;
pstate[count]<=s0;
count<=count+1;
end

else
begin
index<=index+1;
end
end


And this is my testbench:

module DFS_tb();
reg [2:0] in;
reg rst;
reg clk;
wire [2:0] state;

wire [2:0] out;
wire [5:0] visited;
wire [2:0] index;
DFS uut(in,rst,clk,visited,state,index,out);

initial clk=1'b0;

initial
begin
rst=1;
#10 rst=0;
#15 in=0;
end
always #5 clk=~clk;
endmodule


The waveforms are obtained as below.

I expect the index to change at 25ns, but it is getting updated with 1 cycle delay (i.e. 35ns.) I would like to know the reason for this.

• Incomplete code + improper reset logic. You should revisit your fundamentals. Aug 19 '21 at 21:57

You don't seem to be showing us all of your Verilog code...that makes it tough to help you. However, I see that you have the clk and in signals changing at the same time, which can cause unpredictable behavior. Change the transitions of your inputs to be 2 or 3 nanoseconds before the rising clock edge.

Using in and out as signal names is a very bad idea, since these are keywords in Verilog.