1
\$\begingroup\$

Problem: I am looking for options to design a host controller for SSD (SATA or nVME) using transceiver-less FPGA.

Question: What are the current state-of-the-art practices of doing such designs?

My current understanding: I am implying that implementation of MAC and above levels of communication are covered by an appropriate IP-block inside of an FPGA. Then the design requires an external PHY (chip or module) to interface an SSD and a parallel bus between the PHY and FPGA. Examples of such parallel buses are PIPE, as specified by Intel, or a specific DSP-chip interface.

However, surprisingly, the selection of such controllers seems to be very limited: I've found only couple from TI and an obsolete one from Atmel.

So my question is about whether it is reasonable to build an SSD host using transceiver-less FPGA, what interfaces are used to interface PHY and what keywords should I use for a relevant search?

Related: Answers to this question touch on how to transfer data without transceiver on FPGA in general.

\$\endgroup\$
7
  • \$\begingroup\$ I would be looking at SPI based storage devices (SD cards etc) to match with transceiverless FPGAs. SATA doesn't really make sense here. \$\endgroup\$
    – user16324
    Commented Aug 20, 2021 at 14:14
  • \$\begingroup\$ @user_1818839 I agree, but the device needs a mass storage with big volumes, hence SSD. SD card, USB drive or Compact Flash will not suffice. And hence the question about how to mate it with an FPGA without transceivers. \$\endgroup\$
    – megasplash
    Commented Aug 20, 2021 at 16:42
  • \$\begingroup\$ Capacity restrictions should have been in the question. If you need more than 1TB you may have to re-think the transceiverless FPGA. There are some pretty low end devices with transceivers. \$\endgroup\$
    – user16324
    Commented Aug 20, 2021 at 19:10
  • \$\begingroup\$ @user_1818839 You are right, but these are the specifics of a particular design and I intended to keep the question as general as possible. \$\endgroup\$
    – megasplash
    Commented Aug 23, 2021 at 9:38
  • \$\begingroup\$ "SSD host using transceiver-less FPGA, what interfaces are used to interface PHY" Isn't this question anachronistic? You want no transceivers on the FPGA but you want interfaces on the FPGA. \$\endgroup\$
    – DKNguyen
    Commented Aug 23, 2021 at 14:15

1 Answer 1

2
\$\begingroup\$

The answer to the primary question you ask is : yes it is reasonable to use transceiverless FPGAs.

However the answer given the additional constraints is; no it is not.

Long experience tells me that solving an easily solved problem, with the artificial constraint that you cannot use either of the easy solutions, is a losing strategy and a miserable experience all round. There are occasions when an engineer must push back against absurd constraints to save the company time and money. I'll let you judge if this is one of them.

The secondary questions don't really matter.

\$\endgroup\$
1
  • \$\begingroup\$ It doesn't answer my question, which was stated as "how to do this thing?". I still would like to know, what are the options. Nevetherless, thank you for the input, it confirms my initial doubts. \$\endgroup\$
    – megasplash
    Commented Aug 23, 2021 at 16:27

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.