Does VHDL not allow use of the concatenation operator on the LHS of an expression?

Question

This code reproduces the error:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;

entity experiment_1 is
end entity;

architecture beh of experiment_1 is
signal x : std_logic;
signal y : std_logic_vector(2 downto 0);
begin

    process
        variable a : std_logic_vector(1 downto 0);
    begin
        a := "UX";
        x & y <= a & "00";
        wait;
    end process;
    
end architecture;

The x & y <= a & "00"; has same number of bits on both sides but still does not compile. ActiveHDL gives this error:

# Error: COMP96_0015: experiment_1.vhd : (19, 5): '<=' expected.

Answer 1

The target of a signal assignment statement can be an aggregate or a signal name (IEEE 1076-2008 10.5.2 Signal assignment) while x & y is an expression.

You might benefit from perusing the standard or just the VHDL syntax (described in an Extended Backus Naur Form in the standard and useful VHDL books).

Performing an aggregate assignment with objects of different subtypes would require some legerdemain in revisions of the standard prior to -2008:

library IEEE;
use IEEE.std_logic_1164.all;
-- use IEEE.std_logic_misc.all;
-- use IEEE.numeric_std.all;

entity experiment_1 is
end entity;

architecture beh of experiment_1 is
    signal x:   std_logic;
    signal y:   std_logic_vector(2 downto 0);
    type xyrec is record   -- ADDED record type
        x:  std_logic;
        y:  std_logic_vector(2 downto 0);
    end record;
begin

    process
        variable a : std_logic_vector(1 downto 0);
    begin
        a := "UX";
        (x, y) <= xyrec'(x => a(1), y => a(0) & "00"); -- named association or
        -- (x, y) <= xyrec'(a(1), a(0) & "00");   -- positional association
        wait;
    end process;
    
end architecture;

The types of the aggregates are determined by context, here through the use of a qualified expression explicitly stating the type. The context for an assignment statement is the entire statement.

In -2008 or later the type of the elements of an aggregate can be the type of the aggregate itself, a semantic change:

architecture beh1 of experiment_1 is
    signal x:   std_logic;
    signal y:   std_logic_vector(2 downto 0);
begin
    process
        variable a : std_logic_vector(1 downto 0);
    begin
        a := "UX";
        (x, y) <= std_logic_vector'(a, "00");
        wait;
    end process;
end architecture;