I understand that ADC sampling time is the ADC clock cycles for which the sample and hold capacitor is charged up to the channel input voltage. This is a configurable parameter and its value ranges between ns and us.

Let's say I want to read ADC samples for digital signal processing and want to acquire samples at a very specific rate, say 100Hz. I call this the sampling rate. In this case, would it be sufficient if I configure ADC sampling time to be 100Hz to get a sampling rate of 100Hz?

My understanding is that I should configure a timer at 100Hz and use it to trigger ADC conversion, but in this case, isn't it the actual time between two samples i.e the sampling interval would be (10ms(100Hz from sampling rate)+X ns(from samplingtime))?

I am using the ADC of an STM32F4 Discovery board, but my confusion remains the same for any other controller.

What do sampling time, sampling rate and sampling interval really mean?

  • \$\begingroup\$ There's a mux. So you need to allow the input signal to pass through it and update the sample before conversion. To know how long this needs to be you need to read the datasheet for capacitor and resistor values internal to the process as well as know your own source impedances for whatever is driving the ADC pin. And then you will want to wait a sufficient number of \$\tau\$s that you can meet your precision needs. I don't think you've provided enough info for your case. But you are asking instead for an education, I guess? \$\endgroup\$
    – jonk
    Aug 21, 2021 at 6:54
  • \$\begingroup\$ @jonk : Yes, I asked for clearing my confusion. I need to be absolutely sure about sampling interval between 2 sample points for my DSP application. Tirdad's answer clarifies this. \$\endgroup\$ Aug 21, 2021 at 9:31

2 Answers 2


For the case you mentioned, a sampling rate of 100Hz using a trigger and the sampling time of 100ns:

TIMER: TRIG--------------------TRIG----------------
ADC  : SMPL---/DONE------------SMPL---/DONE

The time between 2 consecutive /DONE signals (e.g. conversion complete interrupt) is the same as TRIG signal because the added sampling time is fixed. as long as TRIG interval is bigger than sampling time (+ instruction processing wasted time).

Sampling time is usually used as a limiting value (or a fine tune):

  • (read the jonk's comment). if the current provided by the signal is not much it takes more time for the sample-and-hold capacitor to charge up to the same voltage level as signal. so the more time you give the ADC to sample and process, the better accuracy you get. the best sampling time for accuracy, is the highest one.
  • what if we wanted to sample a signal with an interval of 80ns? the above timings would cause problems so we have to reduce sampling time. we lose accuracy (at least on the LSbits) but we get faster sampling rate. so there is a tradeoff the designer should decide.

EDIT: here are some timings according to STM32F0 datasheet, ADC characteristics:

STM32 ADC characteristics and timings

Which many of them are nearly fixed for some certain setups. the sampling time which is marked, is configured by user. based on this configuration the maximum Rain is provided: Maximum Rain for various sampling times

the sampling times seem to be fixed sufficiently as long as you don't use that dedicated 14MHz ADC clock.

  • \$\begingroup\$ Thanks a lot. I had missed the point that time between 2 consecutive /DONE signals are same. It is clear to me now. \$\endgroup\$ Aug 21, 2021 at 9:26
  • \$\begingroup\$ Yes I've used this method of timer trigger on a STM32F0 for speech processing. the timer triggers ADC on an interval without any software intervention, the ADC triggers DMA on an end of conversion and DMA dumps it in a memory block or uart. \$\endgroup\$ Aug 21, 2021 at 9:44
  • \$\begingroup\$ Is the time between "sampling start" and "result available" really fixed? \$\endgroup\$ Aug 21, 2021 at 10:57
  • \$\begingroup\$ @SimonRichter I edited the answer and added some tables. as long as you have a stable clock and not using that 14MHz ADC-dedicated clock, the table entries are fixed. \$\endgroup\$ Aug 21, 2021 at 17:06

You're a little bit off. You use a timer interrupt to trigger the acquisition. The timer doesn't "tick" at 100Hz, the timer ticks faster than that -- say 10kHz (you get to set all this), and the timer interrupt occurs when the timer interrupts. You preload the counter so that it overflows at the appropriate rate.

The key to all this is that the timer never stops counting. Yes, the acquisition finishes up time delta after the trigger, but while this is going on, the counter preloads the start number again, and just keeps counting -- it doesn't wait for the acquisition to finish -- so your samples are at the correct rate.

The more precision you need, the faster you set your timer tick. You many need a big word, like 32 bits, to make it overflow at a slow enough speed, but there are 32 bit counters on many microcontrollers.

  • \$\begingroup\$ Some STM32 timers have a trigger ability which trigger ADC on a periodic overflow/update event, without any software interventions (e.g. interrupts). \$\endgroup\$ Aug 21, 2021 at 18:26
  • \$\begingroup\$ six of one ... doesn't change principles. \$\endgroup\$ Aug 21, 2021 at 18:28

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