# How to scale (0-7V, 15-18V) to (0V, 3.3V) for OTGW project

## Introduction

There is an open source project for implementation of Opentherm protocol which defines the master and slave circuit for digital communication according to the protocol specification. Opentherm defines a communication protocol between "thermostat" and "boiler" for temperature control of heating and cooling units. The "boiler" communicates by changing current levels and the "thermostat does the same by changing voltage levels of the line. The frequency is 1kHz with min. of 20us rise and fall times.

According to the schematic in the project, the "boiler" circuit defines a constant current source with the ability to change the current between two levels of ~6mA and ~21mA. According to Opentherm specs, the current should be 5-9mA for low level and 17-23mA for high level. At the same time the slave circuit sends messages by changing the voltage on the two lines where:

1. Low level is 0-7V
2. High level is 15-18V

In the following image is shown the "boiler" circuit which illustrates the constant current source, as well as the input(RA0) and output(RA4) connected. The output drives a transistor which changes the current of the current source and the input reads a scaled voltage level from (0-7V, 15-18V) to (0-0.87V, 1.87 - 2.24V). Afterwards, the input is fed into a comparator inside the MCU and converted to digital signal.

This project is very specific, considering the utilization of an inbuilt comparator in the MCU. There is a derivation of this project that should work with 5V MCUs which skips the comparator and connects the line directly to a digital input. Circuit shown below:

According to this circuit, the high levels (15-18V) will be converted to (4.3, 5V) and low levels will be converted to (0-1.63V). Although the levels do not comply with the arduino logic levels, creator of project says that it works. In my opinion, I would increase R8 a bit more so as to decrease the voltage of the low logic level.

## Implementing the circuit for 3V3 MCU

So the goal of this thread would be to adjust the above shown circuit in order to work with a 3V3 MCU. Just to be specific, let's say that we would connect this circuit to an STM32F401 MCU which according to its datasheet requires max. of 0.3Vdd=0.99V for low level and min. of 0.4Vdd=1.32V for high level.

## Example 1

If we go back to figure 1, we would see that the R5 & R6 voltage divider gives (0-0.84V, 1.87 - 2.24V) logic levels which comply with the STM32 datasheet. Theoretically these levels should be within specification and the circuit should work by only using the R5 & R6 voltage divider.

Pros:

• Low cost
• Simple circuit with low number of components

Cons:

• Low margins for error. The 0.15V margin for low level and 0.55V margin for high level is not very convenient. Noise, component tolerance, ambient temperature could be detrimental. Therefore, I don't think this circuit is very reliable.

## Example 2

The inconvenient error margins in example 1 should somehow be avoided and I did a dirty fast solution by integrating a couple of transistors so the levels would swing between 0V and 3.3V. Here is the circuit:

The voltage divider scales the signal to (0-0.48V, 1-1.25V). Since the high level voltage of the divider(R1 & R3) surpasses the Vbe(sat) of the transistor Q1. The transistor will saturate every time there is a high level and the output will be 3.3V. If there is a low level, it won't be enough for Q1 to saturate so there will be ~0.2V on the output. The simulation results are shown below. The Q2 transistor is only an inverter since I didn't want to deal with inverted levels in the software. No doubt Q2 can be avoided.

Pros:

• High margins for error
• The circuit will always convert the defined (0-7V, 15-18V) levels to (0, 3.3V)

Cons:

• Higher cost than example 1
• The circuit does not have hysteresis. The communication line will run with up to 50m distances. All kinds of high(low) frequency noise can be coupled to the line. This noise can lead to false triggering of the circuit every time the signal swings between levels. According to my humble knowledge, any noise faster then the rise/fall times of the signal should introduce false triggering. The typical rise and fall times of Opentherm are 20us. I don't know if this is fast enough to avoid this type of false triggering so maybe someone could share his opinion.

## Example 3

I am not sure if the problem of false triggering in example 2 is really a problem but I decided to go one step further and avoid it by redesigning the whole circuit. Since the original OTGW project uses an inbuilt comparator. I said, why not use an external comparator? This way I can also add a small hysteresis and therefore avoid the problem in example 2.

I defined the following specs for the comparator:

• The (0-7V, 15-18V) input signal will be scaled to (0-1.1V, 2.5-3V)
• The reference voltage of the comparator will be 1.5V
• Hysteresis of ~0.16v will be introduced, which translates to ~1V in the original signal.

According to these specs I designed the following circuit with some resistors that I had available. The parameters are not exactly as the ones defined above but it should do the job.

I was looking for a fast and cheap enough comparator that should do the job. I decided I would use BU5265HFV-TR. The R4 resistor that is used for the hysteresis is large enough to influence the voltage divider. The simulation results are shown below.

According to the results, the circuit defines low and high level voltage between ~9V. The hysteresis is >1V and the output voltage swings between (~0, ~3.3V). Therefore we can say that it roughly satisfies the above defined specs.

Pros:

• High margins for error
• Introduces hysteresis

Cons:

• Higher cost than example 1 and 2

## The question

From my humble experience, I have a feeling that someone much more experienced could think of a much better or cheaper solution compared to example 3. Therefore the question, how to convert (0-7, 15-18V) to (0, 3.3V).

Or maybe if the above solutions are good enough, he could share his opinion on the dilemma of false triggering in example 2.

• If you have a spare analog input, divide by 6 (or so) with a potential divider, connect to ADC, set threshold levels in software.
– user16324
Aug 21, 2021 at 15:06

Please use the following circuitry to replace Q6. The waveform was simulated on LTspice. You need to add one more (at least) BJT in order to get hysteresis. The green trace is 0 - 3.3V output.

Edit
So what else is different? – Phill Donn

Q2 is "Base Common" configuration. The base works like (-) input of a OPA in switching mode, while the Emitter can be cosidered as (+) input of a OPA.
The middle of input threshold-min and trigger-max become 3.3.V by R1 & R5, (please re-calulate R1 & R5, I think, I did not do the work diligently). I kept the input impedance to 20k (R1).:

((Vth - Vtg)/2 + Vtg - Vbe) = ((15V - 7V) / 2 + 7V - 0.7V) + = 10.3V

That is the tipping point, where output transition occurs. Thus, you have noise margin of 4V.

Meantime, since the Q2 Emitter is on 3.3V, you do not need to worry about the over voltage to the input of the microprocessor (assume it is 3.3V IO), while reaching to the rail voltage and provides large noise margin.

Vh_max - Vce_sat = 3.3V - 0.2V = 3.1V

Meantime, for the logic 0, Vlow reaches to 0V, thus, it provides large margin as well. You need to adjust R4 according to your calculation.

All that is done simply by rearranging the configuration, along with PNP in place of NPN.

• This is very similar to example 2 without Q2. Apart from the fact that it is a pnp transistor. Aug 21, 2021 at 17:10
• @PhillDonn , But different, right? What else difference did you notice, in order to get the 0 - 3.3V output? :-)
– jay
Aug 21, 2021 at 17:29
• Well that is all I can see :). So what else is different? Aug 21, 2021 at 18:17
• @PhillDonn , Explained, what I did not explain, in the main text. Please, say it is simple and elegant. :-)
– jay
Aug 21, 2021 at 18:56
• This is definitely better than the case in figure 2 but I still can't see the difference from the circuit shown in example 2. I can see that the voltage divider definitely improves the noise margin between high and low levels. Howver, the IO pin would still be protected from high voltage in example 2 since it would be connected to the collector of the transistor. Aug 21, 2021 at 22:19

The question: From my humble experience, I have a feeling that someone much more experienced could think of a much better or cheaper solution compared to example 3. Therefore the question, how to convert (0-7, 15-18V) to (0, 3.3V), Or maybe if the above solutions are good enough, he could share his opinion on the dilemma of false triggering in example 2.

Considering the cost of failure with a boiler out of control, the savings of copper with a long 2 wire solution, and the ability to provide the possibility of full duplex operation with some immunity to stray EMI (CMRR), there are better ways for improve signal to noise ratio (SNR) and thus the **probability of bit error(**BER) using telephone technology, the 3rd solution looks pretty minimal to accomplish some of of this.

I only see about 25 cents worth of parts there on example 3. (in volume). There must be a slew of interference and susceptibility tests with more parts needed to reject noise and thus reduce errors than what is shown here, but I thank you for sharing an interesting industry protocol solution.

( and that's my two bits worth)

• Would you be kind enough to share any online literature, examples or solutions that could explain the noise rejection requirement part? I know that there is a lack of ESD protection in that circuit as well which in my opinion should be considered as well. Aug 21, 2021 at 17:03
• ESD protection is well covered in here. But to raise immunity from line noise , depending on ambient noise from triac dimmers and SMPS, CM choke for low frequency like a telephony hybrid transformer might be necessary with STP cables and a filter to match the signal BW with 1KHz Biphase to DC but notch line f in extreme cases as the signal is not balanced impedance. A test for CMRR and PSRR ought to be specified for the cable interface and Rx. Aug 21, 2021 at 20:00
• Are you sure that ESD is covered? If you check figure 1 or figure 2, the thermostat connection pins can be exposed to ESD. This would lead to very high voltage on the emitter and base of the Q2 transistor which could lead to damaging. Aug 21, 2021 at 22:02
• I meant ESD in general is covered for all IO cables in the forum Aug 21, 2021 at 23:17