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This is my circuit diagram:

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The bias current of the LM741 op-amp is 80nA. The offset voltage is 1mV.

The LM741 has relatively large current offsets, voltage offsets and input bias. I calculated the error induced in the output voltage, which is 101mV.

I am confused about calculations with the input bias.

80nA * 1MΩ = 80mV. Does this 80mV value mean that this bias current is supplied through this feedback loop? Does this have any significance? Please correct me if I am wrong.

The AC gain would be very large without R2, right? But this concept still appears vague to me: When I removed R2 on my breadboard, the signals on the oscilloscope did not seem to change. How is R2 really useful then?

Also, in another post, I saw that input bias current = 80nA = C dV/dt

Since C=0.1uF,

dV/dt = 800mV/sec.

I am not sure if I understood this correctly. Is this the rate at which the op-amp gets saturated?

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2 Answers 2

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However, I am confused about calculations with the input bias. 80nA * 1MΩ = 80mV. Does this 80mV value mean that this bias current is supplied through this feedback loop. Does this have any significance? Please correct me if I am wrong.

The bias current flowing in the input pins is sourced via the feedback resistor and the input resistor and source impedance. Given that the input resistor is only 10 kΩ and the source impedance might be a few ohms, the effective input offset voltage produced by the 80 nA bias current is more likely to be 80 nA x 10 kΩ = 0.8 mV. If you wanted to account for the fact that some of this bias flows through the feedback resistor then it'll be 80 nA x 10 kΩ || 1 MΩ = 0.792 mV.

This of course may add or subtract with the natural input offset voltage of the op-amp resulting in a range of potential input offset errors of -0.2 mV to +1.8 mV. This value is then multiplied by the non-inverting gain (1 + R2/R1) of 101.

the AC gain would be very large without R2, right?

It's not worth considering; without a natural path for DC current to flow from output to inverting input node (the virtual earth/ground), all bets are off because there is no DC negative feedback.

When I removed R2 on my breadboard, the signals on the oscilloscope did not seem to change.

There was probably some DC leakage path within the chip that kept the output level about the same DC value AND, above a certain frequency, capacitor C1 becomes the dominant component that sets gain whilst R2 becomes irrelevant as a factor as frequency rises.

Also, in another post, I saw that input bias current = 80nA = C dV/dt

Please recognize that you need to supply links to that "other post" so that anyone answering don't have to purchase a crystal ball.

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  • \$\begingroup\$ Thank you! But don't we need to calculate the offset voltage across the feedback resistor like 80nA*1Meg = 80mV? \$\endgroup\$
    – Juye C
    Aug 22, 2021 at 14:33
  • \$\begingroup\$ Also, could you please tell me what is that II symbol called when you wrote 80 nA x 10 kΩ || 1 MΩ = 0.792 mV? \$\endgroup\$
    – Juye C
    Aug 22, 2021 at 14:35
  • \$\begingroup\$ And why do we time the offset voltage with the non-inverting gain? This circuit is a inverting op-amp configuration, so we should times the inverting gain, right? \$\endgroup\$
    – Juye C
    Aug 22, 2021 at 14:44
  • \$\begingroup\$ 1) 80 nA doesn't flow through the 1 Mohm resistor; most of it takes the easier route through the 10 kohm resistor. 2) The 10 kohm (as far as current is concerned) is in parallel (||) with the 1 Mohm resistor. 3) The resulting input offset voltage is in series with either op-amp input and, it's far easier mathematically to assume it's in series with the non-inverting input however, if you did the more complex circuit analysis resulting from assuming it is in series with the inverting input, you'd get the same answer. \$\endgroup\$
    – Andy aka
    Aug 22, 2021 at 14:50
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As you appear to be doing, it is best to calculate the output offset due to input offset voltage and the output offset due to input bias currents separately by setting each to zero in turn and then adding the two effects together.

Let's first assume that the input bias currents are 0nA and assume that the inverting input is 1mV above the non-inverting input. With the input to the amplifier at 0V and 1mV between the op amp's inputs the amplifier's output is forced to go to an offset voltage of 1mV(1+1M/10k) = 101mV.

The input offset voltage is due to manufacturing mismatch between the Vbes of the op amp's input transistors and this mismatch can be either way around which means that the input offset voltage can be either positive or negative. This in turn means that the output offset voltage (due to the input offset voltage) could be either +101mV or -101mV and depends upon the actual op amp in question.

Now let's calculate the output offset due to the input bias currents by assuming that the input offset voltage is 0mV.

The input transistors on the 741 are npn. This means that the input bias currents flow into the op amp's inputs.

The non-inverting input is tied to ground and so the its input bias current has no effect in terms of output offset.

Let's now consider three scenarios, when the amplifier's input is set to 0V, when the amplifier's input is set to +100mV, and thirdly, when the amplifier's input is set to -100mV.

Amplifier's input set to 0V

When the amplifier's input is set to 0V there is no voltage across the 10k resistor and so the bias current must flow through the feedback resistor causing an output offset of 80nA * 1M = +80mV. Remember the bias currents flows into the op amp's inputs.

Amplifier's input set to +100mV

When the amplifier's input is set to +100mV part of the current in the 10k resistor is the input bias current (the current flows "down hill" towards the op amp's input ) and so the current in the feedback resistor has been reduced by 80nA. This creates an output offset of 80nA * 1M = +80mV.

Amplifier's input set to -100mV

When the amplifier's input is set to -100mV part of the current in the feedback resistor is the input bias current (the current flows "down hill" towards the op amp's input) and so the current in the feed back resistor has been increased by 80nA. This creates an output offset of 80nA * 1M = +80mV.

Note that in all three scenarios the output offset due to the input bias current is equal to 80nA * 1M = +80mV.

Now that we've separately calculated the output offsets due to the input bias currents and input offset voltage we can add the the two effects together to obtain the total output offset but because the input offset voltage can be either positive or negative it means that the two offset results can accumulate or partially cancel each other out.

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  • \$\begingroup\$ Thank you very much for your thorough answer, it is interesting to know that the offsets can cancel each other out, too! If they cancel out, does it mean that there are no offset errors in the output? \$\endgroup\$
    – Juye C
    Aug 22, 2021 at 19:22
  • \$\begingroup\$ When the amplifier's input is set to 0V there is no voltage across the 10k resistor and so the bias current must flow through the feedback resistor causing an output offset of 80nA * 1M = +80mV. - and, if that were at all true, by the same token there is no voltage across the feedback resistor because the output is at 0 volts. Please don't confuse the OP. \$\endgroup\$
    – Andy aka
    Aug 22, 2021 at 19:52
  • \$\begingroup\$ Remember the bias currents flows into the op amp's inputs. - not at all true. Take the LM324 for example; 40 nA is the typical current flowing out of the inputs. \$\endgroup\$
    – Andy aka
    Aug 22, 2021 at 19:53
  • \$\begingroup\$ @Fisher Cancellation would mean no output resultant offset errors due to input offset voltage or input bias currents but of course that would be a highly theoretical and unlikely situation. \$\endgroup\$
    – user173271
    Aug 22, 2021 at 20:21
  • \$\begingroup\$ @Andyaka Of course in reality there must be a tiny voltage between the op amps inputs in order for the amplifier to stabalize but I have approximated this input difference voltage to be 0V in order to explain more clearly the output offset voltage being caused by the input bias current flowing in the feedback resistor. That was the point I was trying to make. With regard to your second comment, both the question and my answer were referring to the 741 which I specifically mentioned earlier in my answer. \$\endgroup\$
    – user173271
    Aug 22, 2021 at 20:36

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