Problem stabilizing this PMOS LDO

I am considering a discrete LDO for a supply rail that needs ~$$\m\Omega\$$ impedance at 10 kHz.

While the following circuit does what I need (according to Spice), it becomes unstable if C2 is smaller or R1 is larger.

simulate this circuit – Schematic created using CircuitLab

Question:

• How to stabilize this circuit without crippling its bandwidth ? Inserting Miller capacitors of ~1n near Q5 or M1 helps with stability but greatly reduces gain and increases output impedance.
• Is there a way to reduce DC quiscient current ? I don't need very high gain or low output impedance at low frequencies. I tried replacing R1 with 100k || 1uF. But that node seems to be essentially DC, so the cap has no effect there, and it was unstable.
• Try an emitter resistor of 1 kohm for Q5. You never mentioned what M1 is. Commented Aug 23, 2021 at 12:37
• @Andyaka The emitter resistor had no large effect. larger emitter resistors werent an option due to high input common point. I can check that after lowering input common voltage with a voltage divider. M1 is a generic PMOS of 0.1 .. 1 Ohm Ron. The actual part didnt seem to play a major role for stability so I left it blank. Commented Aug 23, 2021 at 12:52
• I don't like that large value of R2. It reduces your quiescent, but it cripples the drive bandwidth into the FET gate. Try 10k and see how that affects stability. Try a small drain resistor on M1 to make it current output. When a feedback loop has several points where bandwidth is restricted, make one of them low, and push all the others high up in frequency. If all the points have a similar break frequency, that guarrantees instability. Make M1 into C2 the dominant pole if you can, then you can increase C2 without stability problems. Commented Aug 23, 2021 at 13:27
• What dropout voltage do you want, and how much output current? Commented Aug 23, 2021 at 18:20
• @tobalt I wasn't clear. Set your C2 to the minimum you'd ever want, then try to get stability by making it your dominant pole, and push all the other poles up in frequency. Then if you later increase C2, it's fine. You might get some ideas from an LDO-like regulator I cooked up here for a different purpose, C3 providing a bit of lead compensation. Commented Aug 24, 2021 at 12:48

These are my guess, but from nowhere near to LDO design expertise. I borrowed the ideas in the comments, and learned from this thread.
First, the order of reasoning is twisted. And, I would be answering in a random order as well.

The emitter resistor had no large effect. larger emitter resistors weren't an option due to high input common point.

The frequency never (cannot) reached high enough until the M1 Cgs become dominant.

Is there a way to reduce DC quiescent current ? a. Q3 & Q4, eventually R1, are responsible for the large quiescent current.

I tried replacing R1 with 100k || 1uF. But that node seems to be essentially DC, so the cap has no effect there, and it was unstable.

That DC is because R1 is saturated. That is due to Q3 Q4 configuration, reduce the current through Q3 & Q4, until R1 can take large value. 1uF there is not good, kills the BW at the input (diff) stage, end up in more oscillation.

larger emitter resistors weren't an option due to high input common point.

Again, that "emitter resistor" and Q3 & Q4 has to be re-balanced, in order to allow a large resistance, by re-configuring Q3 & Q4.

Once that diff stage gets settled, level-shift/bias (? Q5 & R2) and the gain stage (M1, "gm" ?) will need to be settled.

In short; Q5 takes a portion of the current from the current mirror (Q3 & Q5), that makes up the voltage on R2. I would attain correct voltage level (bias) on M1 gate. The reasoning behind is that, the gain (AC) is decided by gm stage, by the effort of Q5 driving (charging, discharging) M1 gate, which become the gate voltage.

After that has been arranged, with the question related to C2 value:

The gain of M1 depends on the current, from M1 drain this time, through the load. Meantime, Q2 is taking too much current to the base, effectively lower impedance comparint to C2. That is how you see a larger cap helps.

Edit

Below is the screen capture, tested at 15V input. load 1mA - 5A (4 times of 5sec sweep, output cap 0.1uF (works for 0 to 1000uF). The quiescent current for 5A circuitry takes about 1mA. Meantime, 1A circuitry can be done with about 500uA.

Fig. 1, set to 15V (0V drop out) : ripple = 0.4V

Fig. 2, set to 14.8V (0.2V drop out) : ripple = 0.24V

Fig. 3, set to 14.5V (0.5V drop out) : ripple = 0.04V

Fig. 4, set to 5.0V : ripple = 0.02V

Fig. 5, set to 14.6V (0.4V drop out), compared to GND : ripple = 0.07V

Fig. 6, The circuitry

Q1, Q2: Diff input
R1, Q3, Q4: Bias current
Q5, Q6,Q7, R2: Level shift
Q8, Q9: Buffer (I forgot what to name it)
R7, R9, C3: Feedback
R11, C2: gm input (not sure if that really works as I like).
M1: The output driver, gm

It took some time. It is my design, and license free.

• I'd like to go through your suggestions but I have trouble understanding. What do you mean by reconfigure Q3/Q4 for lower current, which would allow a larger R1 and larger emitter resistor on Q5? If I increase R1 (reduce the current through the mirror), the thing becomes unstable. The 1 uF around R1 doesn't decrease bandwidth. I had hoped it would increase it by allowing more supply current at higher frequencies, but it simply has no effect. Commented Aug 24, 2021 at 11:37
• @tobalt, the main reason is that Q3 & Q5 cannot stay on the high side, in my opinion. I would move them to low side, NPN, split and move R1 to the high side. Set the Q3 Q5 current very very low. Probably, I have to re-word my sentences. However it is, get the diff amp work with low current, swinging nice at the high side. Then, make correct level shift to bias the FET, then use the FET gain. That is what I would do. I have done similar work, but many years ago. It will take a day or so to come up with a practical circuitry to begin test. I will try to correct my posting, otherwise remove it
– jay
Commented Aug 24, 2021 at 22:35
• "1uF around R1", you made the point... I will think about that.
– jay
Commented Aug 24, 2021 at 22:47
• @tobalt , updated the answer. Please, take a look and let me know of your opinion.
– jay
Commented Aug 25, 2021 at 3:34
• Thanks for the work. I'll analyse the circuit when I find the time :-) As you focus on DC load regulation (which appears to be on the order of 10 mOhm), what is that like for ~10 kHz. Could you perhaps add a small signal output impedance plot vs frequency ? Commented Aug 25, 2021 at 7:53

1mOhm @ 10kHz ; Accuracy, noise, settling time are all pretty irrelevant. it needs only to source current. doesn't need short circuit protection (is precent at other places). the most critical freq. band is 10kHz..50kHz. For lower freqs, the impedance can be gradually higher because the PSRR of the load will be higher. load is a few ICs and decoupling caps. the LDO will sit right at the load connected through a short polygon/pour. output cap should be one cercap. of course one could use something like 5 Al poly caps instead of the entire LDO but that's what I'm trying to avoid

OK. In the past I've done a regulator with an output impedance of 0.4nH as a challenge project.

If you want low output impedance at mid-frequency like 10kHz you will need quite a lot of bandwidth. This means the most critical thing is how the output impedance of the LDO interacts with the impedance of the caps.

Here L2 is the output impedance of the LDO. With 3x 1µF MLCCs of typical low ESR the caps have a capacitive impedance up to a few MHz, then quickly flip to an inductive impedance above this. Since the LDO will lose open loop gain as frequency increases, its output impedance is usually inductive, so I've used L2 to model it. As expected, there is a huge impedance peak where the inductive impedance of the LDO meets the capacitive slope of the caps, which means it is unstable. This is usually what happens when using a low-ESR cap on a LDO that is not rated for low-ESR caps.

There is only one way to make it stable, that is to increase the damping factor by adding resistance somewhere, for example in the output impedance of the LDO:

This is how some LDOs like ADP151 work. They have a highish output impedance with a nice resistive (real) part which makes them super stable with ceramic caps. But that doesn't suit your project.

To get better DC regulation and load transient response, some LDOs put a bit more work in synthetizing an output impedance that is resistive above 100kHz, but inductive below, so it drops to a very low impedance at DC.

That works very well with ceramic caps, but the impedance bump around 400kHz is where you don't want it, since it increases impedance at 10k. One solution would be to use more MLCCs on the load, but at 15V that's gonna be a lot of them. That's with 30µF of MLCCs:

The impedance transition modeled by L3//R3 can also be created with a low ESR polymer capacitor, but you want to avoid that. So I tried with 3x 100nF decoupling caps, and 2x 1µF "bulk" caps with 0R33 resistors in series. This seems to work nicely.

At 15V, 100nF X7R 0603 and 1µF X7R 0805 hold their capacitance nicely, but the 10µF caps do not, they lose too much capacitance with increasing voltage. You can get C-V curves on Murata website for example.

The last solution to add damping resistance is to add ESR to the ceramic capacitors, but the resistor will increase their inductance.

Anyway.

I went with 3x 1µF MLCCs on the load. The pass transistor has to be a BJT because at low Vds, capacitance of MOSFETs increases a lot, which makes them very slow. LDOs tend to use FETs for efficiency because the base current is not wasted, but I guess you're not going for ultimate efficiency here.

Compensation network C31/C33/R5 tweaks the output impedance to give it some resistive impedance around 1MHz for smooth transition to the MLCCs.

I've tweaked the feedback network a bit so the differential pair has enough Vce to work.

Output impedance depends on load current, because gm and fT of the pass transistor does. So it still needs an aluminium cap to ensure low load stability.

It works... barely. 10µF caps on the output would be preferable. A fast opamp instead of the differential pair would solve a lot of problems.

But I hope you got the idea that what determines the low frequency impedance of your LDO is how its output impedance will meet the impedance of the decoupling caps.

• Wow what a deep analysis. I've found many similar results in my analysis, such as stabilizing it all with copious ceramic output caps. But especially your final schematic provides a lot of stimulation for further testing. Thanks a lot! Commented Aug 24, 2021 at 11:13
• Thanks! It helps if you plot the LDO output impedance like I did in red: I put a zero ohm resistor in the output (R4) and plot V(out)/I(R4). Same with the caps, you can plot V(out)/I(cap). So you can see how the two intercept: visually, a 45° angle on the dB plot means 90° phase shift between the two so it's good, R versus L or C versus R gives no problem, 90° angle means 180° phase shift, L versus C, and trouble. Commented Aug 24, 2021 at 12:11

After some research I figured that a simple Flipped Voltage Follower LDO circuit does what I need:

The schematic shows only the central components. V++ is 15 V. Vrail is around 14.5 V. The AC plot shows the output impedance in Ohm when sourcing around 200 mA.

The peak and dip near 1 MHz are due to a load capacitor of 5µF. The regulator is (very) stable with or without this capacitance as indicated by the phase plot.

The increase towards low frequencies are due to the impedance of V++. There is an LC filter with half an Ohm of series resistance, which affects Vref and thus Vrail. If necessary, DC regulation can be improved greatly by using a Zener instead of a resistor divider to derive Vref.

The transistor selection is very uncritical. MOSFET VGS,th should be at least 1 V and have low enough Ron to allow for the set dropout voltage at maximum current. The gate capacitance forms the dominant pole at ~10..100 kHz, so it should not be a needlessly large MOSFET.