These are my guess, but from nowhere near to LDO design expertise. I borrowed the ideas in the comments, and learned from this thread.
First, the order of reasoning is twisted. And, I would be answering in a random order as well.
The emitter resistor had no large effect. larger emitter resistors
weren't an option due to high input common point.
The frequency never (cannot) reached high enough until the M1 Cgs become dominant.
Is there a way to reduce DC quiescent current ?
a. Q3 & Q4, eventually R1, are responsible for the large quiescent current.
I tried replacing R1 with 100k || 1uF. But that node seems to be
essentially DC, so the cap has no effect there, and it was unstable.
That DC is because R1 is saturated. That is due to Q3 Q4 configuration, reduce the current through Q3 & Q4, until R1 can take large value. 1uF there is not good, kills the BW at the input (diff) stage, end up in more oscillation.
larger emitter resistors weren't an option due to high input common
Again, that "emitter resistor" and Q3 & Q4 has to be re-balanced, in order to allow a large resistance, by re-configuring Q3 & Q4.
Once that diff stage gets settled, level-shift/bias (? Q5 & R2) and the gain stage (M1, "gm" ?) will need to be settled.
In short; Q5 takes a portion of the current from the current mirror (Q3 & Q5), that makes up the voltage on R2. I would attain correct voltage level (bias) on M1 gate. The reasoning behind is that, the gain (AC) is decided by gm stage, by the effort of Q5 driving (charging, discharging) M1 gate, which become the gate voltage.
After that has been arranged, with the question related to C2 value:
The gain of M1 depends on the current, from M1 drain this time, through the load. Meantime, Q2 is taking too much current to the base, effectively lower impedance comparint to C2. That is how you see a larger cap helps.
Below is the screen capture, tested at 15V input. load 1mA - 5A (4 times of 5sec sweep, output cap 0.1uF (works for 0 to 1000uF).
The quiescent current for 5A circuitry takes about 1mA. Meantime, 1A circuitry can be done with about 500uA.
Fig. 1, set to 15V (0V drop out) : ripple = 0.4V
Fig. 2, set to 14.8V (0.2V drop out) : ripple = 0.24V
Fig. 3, set to 14.5V (0.5V drop out) : ripple = 0.04V
Fig. 4, set to 5.0V : ripple = 0.02V
Fig. 5, set to 14.6V (0.4V drop out), compared to GND : ripple = 0.07V
Fig. 6, The circuitry
Q1, Q2: Diff input
R1, Q3, Q4: Bias current
Q5, Q6,Q7, R2:
Q8, Q9: Buffer (I forgot what to name it)
R9, C3: Feedback
R11, C2: gm input (not sure if that really
works as I like).
M1: The output driver, gm
It took some time. It is my design, and license free.