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I am trying to choose a transistor to use in a current mirror to prevent thermal runaway of parallel LEDs (yes I have to connect them in parallel. I know connecting in series or using separate constant current drivers would solve this but it is not possible in the design.)

I need to fully saturate the transistor to ensure the LEDs are being driven by the correct forward current.

On Semi CPH6539-TL-H datasheet- VCE saturation typical and max voltage

The datasheet states that the typical VCE(sat) is 0.16V and max 0.25V. Looking at the Ic-VCE graph, at 0.16V, the device does not appear to be saturated (with the saturation region being where the graph is 'flat' or 'levels out.') Why does the datasheet state that the saturation voltage occurs when VCE=0.16V (to a maximum of 0.25V) but the corresponding graph does not agree with this?

Ic Vce curve

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  • \$\begingroup\$ Saturation in an NPN BJT is when Vbe is > 0 V and Vbc is > 0 V at the same time. In other words when both base-emitter and base-collector junctions are forward biased. In my opinion this is the best way to think of it. NOTE: you actually do not want to operate your current mirror in saturation, even though you think you do. If it is saturated it will not be working correctly. \$\endgroup\$
    – mkeith
    Aug 23, 2021 at 21:45
  • \$\begingroup\$ @mkeith Why would you not want to operate the current mirror with all transistors fully saturated? If the base is tied to the collector, therefore no current limiting resistor, then the transistor will automatically be fully on and saturated? \$\endgroup\$
    – MRB
    Aug 23, 2021 at 21:50
  • \$\begingroup\$ @mkeith I already have a constant current source driving the parallel branches of LEDs and the purpose of the current mirror is to share the current equally. I need to make sure my voltage regulator has enough voltage to provide the LEDs rated voltage and fully saturate the transistor. I do not want there to be insufficient voltage which causes the LEDs not to get the rated voltage because some is taken by the transistors. \$\endgroup\$
    – MRB
    Aug 23, 2021 at 21:55
  • \$\begingroup\$ @MRB I'm just skimming. BJT current mirrors are not operated in saturation -- one of them can't be and the other should not be. You can do force one of them to do it (the one with the load attached), but you don't want to because, smashed up against its emitter it's just a voltage source then and no longer a current source. In short, it no longer performs the function you ascribe it. So it's no longer a current mirror, then. \$\endgroup\$
    – jonk
    Aug 23, 2021 at 22:02
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    \$\begingroup\$ The current mirror will enforce equal sharing between two strings. However, when the base is connected directly to the collector, the transistor will not be in saturation because Vbc will be 0V (since they are connected together). You should not plan for Vce to be equal to Vce(sat) in a working current mirror. Instead Vce and Vbe will be the same, and will be equal to one diode drop (something like 0.6V or 0.8V depending on how large Ic is and individual transistor characteristics and temperature). \$\endgroup\$
    – mkeith
    Aug 23, 2021 at 22:04

5 Answers 5

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Your interpretation of the \$V_{CE}\$ vs. \$I_C\$ curves is incorrect. That graph shows the behaviour of the transistor in isolation, where \$V_{CE}\$ is varied, and the resulting \$I_C\$ is plotted. The flat regions are in fact where the transistor is operating in its linear region.

If you extend the horizontal axis to the right, you obtain curves like these:

schematic

simulate this circuit – Schematic created using CircuitLab

The straight flat-ish regions of the \$I_C\$ vs. \$V_{CE}\$ curves aren't actually flat - they are sloped, such that they all intercept the horizontal axis at approximately the same voltage, called the Early voltage. This is called the Early Effect. Importantly, the slope (change in collector current divided by change in collector-emitter voltage, \$\frac{\Delta I_C}{\Delta V_{CE}}\$) is different for each different base current. This slope is called admittance, and is the reciprocal of the effective small-signal resistance between collector and emitter. The important point here is that in this region, the transistor is not saturated, and is in fact amplifiying linearly.

The region of this graph that corresponds to saturation is where the curves are near-vertical. In the classic collector resistor and fixed voltage source scenario, this occurs when the resistor has the maximum voltage across it, and further increases in base current cannot result in any rise in collector current:

schematic

simulate this circuit

In this scenario, where collector current has reached a maximum, variations in base current are analogous to jumping horizontally (because \$I_C\$ is fixed) from curve to curve in the \$V_{CE}\$ vs. \$I_C\$ plot.

From your graph, if \$I_B\$ is 15mA, and \$I_C\$ is 750mA, then we are clearly sat in the "vertical" region, and the transistor can be said to be saturated. At that point, the graph shows us that \$V_{CE}\$ will be 0.16V.

If you were then to increase base current \$I_B \$ from 15mA to 20mA (and assuming this doesn't alter \$I_C \$ significantly), this would represent a jump horizontally to the left, from the 15mA curve to the 20mA curve, and you can see that \$V_{CE}\$ would drop from 0.16V to 0.15V. That should help illustrate that a large increase in base current has not resulted in any significant change to \$V_{CE}\$, because the transistor is saturated in this regime.

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  • \$\begingroup\$ This explanation helps my general understanding of the Ic-Vce graph, I now understand why my original line of thinking was incorrect. Am I correct in saying that because I will have the transistors in a current mirror, with the base tied to the collector, the transistor will not be saturated and instead be in between saturation and forward active region example here? Am I correct in saying that the volt drop from collector to emitter will be 0.6-0.7V? \$\endgroup\$
    – MRB
    Aug 24, 2021 at 9:12
  • \$\begingroup\$ @MRB The "ref" transistor will have \$V_{CE}=0.7V\$, but the other \$V_{CE}\$ will be free to vary from 0.1V (saturation) upwards, depending on transistor and load impedance matching. \$\endgroup\$ Aug 24, 2021 at 9:50
  • \$\begingroup\$ If the other Vce can vary from 0.1V upwards, how do I calculate what supply I need to ensure that the LEDs are supplied with exactly the right voltage? If the Vf(LED) is 2.6V for example, the ref transistor will need a resistor with 2.6V across it and 0.6-0.7V across the transistor itself to set up the current mirror. This means the supply would need to be 2.6+0.7=3.3V. In the LED branch, if the transistor has o.7V across it then the LED will have the correct 2.6V across it. But if Vce varies down to 0.1V as you said, then the voltage across the LED will increase to 3.2V. \$\endgroup\$
    – MRB
    Aug 24, 2021 at 10:08
  • \$\begingroup\$ @MRB I believe your best bet here is to ask another question on SE, because this is another topic, and the answer is more complicated than can be summarised here. Do that, with a rough schematic, and link to it here - I'll answer you "on the other side". \$\endgroup\$ Aug 24, 2021 at 10:21
  • \$\begingroup\$ Done New question here \$\endgroup\$
    – MRB
    Aug 24, 2021 at 11:28
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The term "Saturation" means exactly the opposite for FETs and BJTs. The flat region is not in saturation for junction transistors. A transistor in saturation would be at the bottom left corner.

By "Saturation voltage" they mean the collector to emitter voltage under the given conditions. Usually it is with a forced beta of 10 or 20. In the datasheet segment you show it is with a forced beta of 50.

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The curve tracer type slopes show constant base current with Vce vs Ic. But the horizontal slope acts as a (lossy) current sink and the more vertical slopes act as a lossy switch (resistor).

enter image description here

(sorry for quick and dirty curves added to show hFE and Rce(sat) with the current ratio)

Vce(sat) tends to be rated at 10% of the max linear hFE . But some transistors have hFE > 1000. This one is 200 typical in the low current range but only 80 in the 20 mA range. However they rated Vce(sat) at 50:1 current ratio.

Question:

why does the datasheet state that the saturation voltage occurs when VCE=0.16V (to a max of 0.25V) but the corresponding graph does not agree with this?

The graphs show it but it is only one point in magenta. For efficiency reasons, they chose the optimum current ratio within reasonable heat rise. This turns out to be about 10% of the max linear hFE ratio when used as a current amplifier.

Then the steepest part of the curves are the lowest resistance as a switch. The rated Vce(sat) is just to the right of the steepest curve where the Rce changes from 180 mΩ to 333 mΩ with a higher current ratio.

Other

Question not asked is ...

How do you choose a LED switch for 3.3V when the LED uses up 3.1V and the Vce(sat) is > 0.2V

Compute required Rs for current sensing or voltage drop and choose a FET switch with much lower resistance.

e.g. 50 mOhm FET regulated by a 50 mV current sense shunt at max current and an Op AMp to regulate the FET bias so you get < 100mV drop total. with 100 mV margin.

You pick your own values for V margin and current and RdsOn.

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1. BJT Saturation vs. Active Region

  1. Reference link:

http://home.iitj.ac.in/~sptiwari/EE314/Lecture8_BJT.pdf

  1. Image:

enter image description here

Relative to the emitter, as shown for the pnp transistor, when the base-emitter voltage is greater than the collector-emitter voltage the BJT device is operating in the saturation region.

2. The Diode-Connected BJT

  1. Reference:

https://inst.eecs.berkeley.edu/~ee140/fa19/dis/01/current_mirrors.pdf

  1. Image:

enter image description here

3. Compliance Voltage of Current Source or Current Sink

This video ends with a demonstration of driving LEDs with a current source where the limit on this ability is called the compliance voltage:

https://youtu.be/xR0RfmmRhDw?t=997

It sounds like you want to operate multiple strings of LEDs in parallel from a fixed minimum voltage source and program all strings to have constant current. I don't think you have to saturate transistors for this design, however, your voltage source must exceed the minimum compliance voltage of each current source or current sink.

In fact the video lesson effectively ends on this statement "In this case the compliance voltage is reached when we saturate the transistor."

So the transistor current source or current sink is operating in the active region as a variable resistor and is not operating in the saturated region.

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It seems you are mixed up about what saturation is and perceive a contradiction where there is none.

Saturation in a BJT is where the base emitter junction and base collector junction are both forward biased.

In the datasheet in your question, note that the conditions given for Vce(sat) are Ic = 0.75 A and Ib = 15 mA. Here is the graph with that particular point marked with a red cross.

enter image description here

As you can see, the vertical red line crosses the horizontal axis at about Vce = 0.17 V. This is within the range given by the datasheet, so there is no contradiction. You were perhaps just confused about which part of the graph shows saturation.

Also, in a current mirror, the transistors are NOT saturated in normal operation when the mirror is working. And in fact, for the mirror to work correctly, saturation must be avoided. You should probably allow something like 1V for Vce to make sure the current mirror does not saturate. Also, you may want to add a small resistor in series with your reference side of the mirror to make sure minor variations do not cause the non-reference side of the mirror to saturate when you don't want it to.

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