The output update rate (also commonly referred to as the clock rate) of a DAC lets us know how fast the DAC can accept new digital input words. Words are transferred on to the output of this DAC at whatever rate they are input, as there is no buffer on this DAC device. There will not be a backlog of digital values that builds up over time.
The data sheet shows that the DAC is guaranteed to work for sample rates of at least 125 MSPS with a 3 V power supply or 165 MSPS with a 5 V supply, so running at at 100 MSPS is well within the DAC capability.
The DAC dynamic performance (SFDR, THD) is specified at 100 MSPS (and higher) in the data sheet. Achieving this performance will be possible, given a well designed application circuit and PCB.
For a step change in value, the DAC output is guaranteed to settle to within 0.1% of its final value within 30 ns. If the DAC value is changed before 30 ns, the output may not completely settle to the 0.1% level, but the output will be driven to a level that is close enough to support the dynamic specs mentioned above.