I need a fast DAC that can receive and update values once every 10ns (which are received from an FPGA). Naturally, I looked for a DAC with a 100MSPS rating. However, I noticed that the settling time for this DAC is 30ns which doesn't make sense to me. How can it sample digital values faster than it can output them?

I would expect a backlog of digital values to continuously grow.

The specific DAC I'm looking at is the DAC908E which actually has a minimum of 125MSPS and a maximum of about 200MSPS with a settling time of 30ns.

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    \$\begingroup\$ Settling time is an analog parameter that describes how long it takes the output to stabilize after it changes. It does not limit sampling rate, only bandwidth. \$\endgroup\$ Commented Aug 24, 2021 at 3:14
  • \$\begingroup\$ @user1850479 so if I understand correctly, the sampling time determines the range of signal frequencies that the DAC can reconstruct? Which would mean this DAC can accurately reconstruct signals that are up to 33 MHz ? \$\endgroup\$
    – Andrew
    Commented Aug 24, 2021 at 3:21

2 Answers 2


The output update rate (also commonly referred to as the clock rate) of a DAC lets us know how fast the DAC can accept new digital input words. Words are transferred on to the output of this DAC at whatever rate they are input, as there is no buffer on this DAC device. There will not be a backlog of digital values that builds up over time.

The data sheet shows that the DAC is guaranteed to work for sample rates of at least 125 MSPS with a 3 V power supply or 165 MSPS with a 5 V supply, so running at at 100 MSPS is well within the DAC capability.

The DAC dynamic performance (SFDR, THD) is specified at 100 MSPS (and higher) in the data sheet. Achieving this performance will be possible, given a well designed application circuit and PCB.

For a step change in value, the DAC output is guaranteed to settle to within 0.1% of its final value within 30 ns. If the DAC value is changed before 30 ns, the output may not completely settle to the 0.1% level, but the output will be driven to a level that is close enough to support the dynamic specs mentioned above.

  • \$\begingroup\$ So would that imply that this DAC could "reconstruct" a signal with a maximum frequency of ~30Mhz (1/30ns)? \$\endgroup\$
    – Andrew
    Commented Aug 24, 2021 at 4:12
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    \$\begingroup\$ That depends on what fidelity you need in your "reconstruction". If your application absolutely demands a reconstruction that requires dc settling to the 0.1% level, you will be limited to 33 MSPS. I would suspect that most applications do not require DC settling to this level. \$\endgroup\$
    – B Pete
    Commented Aug 24, 2021 at 4:21
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    \$\begingroup\$ @Andrew If your 3dB bandwidth is 170 MHz, then at 30 MHz you are attenuated by ~0.1dB. Do you need better than 0.1 dB accuracy? If so, either buy a faster DAC (that one is a few bucks in bulk, so anchor your expectations), or else apply equalization to your signal to compensate. If you require such extreme accuracy, you may actually need to do both and then calibrate your system, as capacitors are usually only 10% accurate anyway. \$\endgroup\$ Commented Aug 25, 2021 at 1:06

Settling time is defined (by that data sheet) as the time required for the output to stabilize to 0.1% of the final value. Since the DAC doesn't have infinite bandwidth, this value will not be zero and it'll take some time for the output to actually change. Since 0.1% is a very small value, it'll take multiple samples to get there.

More commonly bandwidth is specified in terms of the 90-10% rise/fall time. The datasheet specifies 2 ns for that. If you assume a 1st order RC roll off, the 3dB bandwidth is 0.34 divided by the rise time, or 170 MHz.

A more detailed derivation is available here: https://en.wikipedia.org/wiki/Rise_time


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