After recently acquiring an MSP430 Launchpad I've been playing with various microcontroller projects. Unfortunately, the MSP430G2553 only has 512 bytes of RAM, so doing anything complex requires external storage.

After looking at SPI and I2C SRAM and EEPROM chips, I discovered FRAM.

It looks perfect. Available in large sizes (the one linked to above is a 2Mb part), low power, byte addressable and programmable, nonvolatile, no wear issues, no need to explicitly erase anything, and actually cheaper than serial SRAM (comparing against Microchip's parts).

In fact, it looks too perfect, and that makes me suspicious. If this stuff is so much better than serial SRAM and flash EEPROM, why isn't it everywhere? Should I stick with SRAM, or is FRAM a good choice for experimentation?

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    \$\begingroup\$ If they could match the density of standard flash for a similar cost/bit then there would not be any flash. \$\endgroup\$
    – Kortuk
    Commented Feb 18, 2013 at 1:02
  • \$\begingroup\$ The foundry process may be expensive and may not be possible to integrate with existing micros.To integrate FRAM into micros (monolithic), they need to be ported to the foundry process that would support FRAM and the microcontroller block (logic). It is time consuming and tedious. \$\endgroup\$ Commented Feb 18, 2013 at 1:57
  • \$\begingroup\$ @ChetanBhargava they also dont have the same density. MSP430s have been discussing releasing a chip with all FRAM for a while, since you can use it as your ram and your rom and your chip will not loose state with a restart. \$\endgroup\$
    – Kortuk
    Commented Feb 18, 2013 at 2:18
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    \$\begingroup\$ The msp430 "F" sub-family of microcontroller might be useful to consider, they have integrated FRAM. Also, the Value Line devices mentioned are entry level introductions to the family, there are other Texas Instruments MCUs with considerably higher specifications. \$\endgroup\$ Commented Feb 18, 2013 at 2:21
  • \$\begingroup\$ @Kortuk that is right. Last time I met Mark Buccini (TI-MSP430) we discussed this as TI had just put in lots of interest in Ramtron. This was a while ago. \$\endgroup\$ Commented Feb 18, 2013 at 2:23

4 Answers 4


From what I can see, the (main) difference between it and SRAM is it's slower, and the difference between it and EEPROM is it's more expensive.
I'd say it's sort of "in between" both.

Being a pretty new technology, I'd expect the price to drop a fair bit over the next year or so providing it becomes popular enough. Even though it's not as fast as SRAM, the speed is not bad at all, and should suit many applications fine - I can see a 60ns access time option on Farnell (compared with a low of 3.4ns with SRAM)

This reminds me - I ordered some Ramtron F-RAM samples quite a while back, still not got round to trying them yet...

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    \$\begingroup\$ Is that SRAM speed serial or parallel? Because if it's serial that's seriously fast. The FRAM part I'm looking at claims to do zero-latency writes via SPI at 40MHz, which is faster than my microcontroller's clock speed... \$\endgroup\$ Commented Feb 18, 2013 at 12:42
  • \$\begingroup\$ It's parallel (here's an example) and I compared it to the parallel F-RAM options (example. If you are looking for an SPI part then with the faster parts you will be limited by the maximum SPI speed rather than the read/write times. If the non-volatile feature is useful for your project, and the speed is adequate I think I'd give the F-RAM a go. \$\endgroup\$
    – Oli Glaser
    Commented Feb 19, 2013 at 14:09

FRAM is great, however, the technology has destructive reads. Flash technology has a limited write/erase cycles, but the reading cycles are almost unlimited.

In FRAM, each read cycle actually affects the memory and it starts to degrade. TI states that they've found the FRAM has "Wear-out free endurance to 5.4 × 10^13 cycles and data retention equivalent of 10 years at 85°C". After some calculations this turns out to be around 2 years of constant read cycles or so (without taking into account ECC).

The reality is that for most low power applications, where duty cycles are low, this is not an issue. You will need to evaluate it for your specific application.

The limit in speed is also present, so waitstates will be added if needed. However, one solution is to load code to RAM, run it from there (avoiding the cycles on the FRAM) and avoiding the speed limit.

There was an E2E post on the topic here that discussed some of the ramifications.

A good App Note from TI about what the advantages of FRAM are as far as security is Here

  • \$\begingroup\$ That thread is a bit contradictory, alas --- not only does it depend on the kind of technology (and I don't know what technology the Cypress/Ramtron part is), but one guy suggests that you can work around read degradation by writing to it! Either way it's not relevant to me because I won't be driving it that hard, but it's worth knowing --- ta. \$\endgroup\$ Commented Feb 18, 2013 at 12:30
  • \$\begingroup\$ @DavidGiven: I put it up because it had Jacob from TI's marketing answering. From what I know, there are many people using FRAM due to its advantages, despite the destructive reads. \$\endgroup\$ Commented Feb 18, 2013 at 15:08
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    \$\begingroup\$ Your spec on wear endurance completely ignores all practice with using such devices and makes no sense. It is RAM, if all you are going to do is read the same bit over and over, why not use Flash? If you read/write cycling through every cell of a 16K FRAM part at 20Mhz SPI, you'd need 84 years to wear it out. \$\endgroup\$
    – iheanyi
    Commented Jan 11, 2017 at 20:51
  • \$\begingroup\$ Destructive read sounds so harsh. But yes, technically this is correct, a read cycle must be counted against the FRAM's endurance spec. For TI-fabbed Ramtron/Cyp devices, the spec has been 1E14 (@85C) for many yrs now. In reality even very read/write intensive applications would never come close to reaching 1E14 cycles (actually 1E16 . And BTW, this is a read/write cycle that a specific byte experiences, not any random cycle (other cells). The datasheets include an example calculation for endurance estimates. For serial 'V' FRAMs the limit is virtually unreachable, as iheanyi points out. \$\endgroup\$
    – gman
    Commented Oct 12, 2017 at 17:49

The only real issue with FRAM is that for the really dense parts, the part of the market that drives volume and margin, they cannot yet compete on density (which is either a yield thing or a size thing - it doesn't really matter which). For the smaller parts (i.e. competing against older version of same technology) they do well.

So yes, it's a good fit for experimentation as long as you stay in the same size parts.


If some (insert semiconductor corporation) develops a process of increasing the density of FRAM, it could replace DRAM. While marginally slower than SRAM, this could upend the DRAM industry for being a cheaper, more performant alternative to our main memory in PC's, DRAM.

Considering the widening CPU to Memory Speed/Bandwidth gap problem - FRAM as I see it developed in competition directly with DRAM - is solved. It also uses the least amount of power of all memories, which means for the same volume we can extract more "power/speed" or potentially "capacity".

Also - FRAM has the highest endurance of all memories (Flash, EEPROM, etc) in a NVM (Non-Volatile Memory) use case. By an order of magnitude. I believe a few orders of magnitude really!

In a volatile use case, the destructive reads are irrelevant. Data retention is guaranteed for years and years when they quote the endurance of the NVM memories. What about the potential need for retention to only be milliseconds or less?

There is no catch!


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