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I was going through an article related to SPI. There was a configuration named 'Daisy Chaining', in case of multiple slaves. So far, what I have understood about SPI (based on Wikipedia) is:

SPI can transfer and receive some data simultaneously.

My questions are:

  1. In case of multiple slaves, does it mean, that it transfers data to many slaves, or it transfers data to one of the slaves, amidst a connection to many slave devices?

  2. According to Application note 3947, Daisy-Chaining SPI Devices, figure 4, it is given that, the master keeps its SS low, until all the data it needs to send to the three slave devices is sent and then it makes the pin high. If so, what data & from which slave device, does the master receive at the end? (As, I've learnt that, the master always receive something in return.)

  3. As stated in Architecture and programming of 8051 MCU's, in enhanced mode the load enable (LDEN) & WCOL is checked for moving the next byte into the buffer. Why do we need to check them both? Isn't the WCOL sufficient for that?

  4. It's states: "Master configures the clock - frequency less than or equal to the maximum frequency the slave device supports. Such frequencies are commonly in the range of 1–100 MHz." How does the master find the clock frequency of the slave?

  5. Does the SPSR, SPCR and SPDR registers remain in both master and slave?

  6. It is given that, the SPIF flag is set after the completion of transmission. If the SPIE is also enabled, then an interrupt is produced. Does the flags get set in both master and slave? Is the interrupt produced in both master and slave? It's stated in AVR151: Setup And Use of The SPI about interrupts in both master and slave. But, I couldn't understand it clearly.

  7. What is the application-oriented difference between the normal mode and enhanced mode? Both seem to wait for data to send/receive. What's the main difference?

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A few points. That Maxim article targets a specific type of spi device. Mainly ones that are write only. Notice only MOSI is shown, not MISO. Additionally, these devices are chained, so data is shifted from one device to the other, like a shift register. (One common use of SPI peripherals on a microcontroller is to use them to drive common shift registers.)

SPI does not require the master to receive data. A slave is not required to respond. You can even have read only SPI devices, where the Master just clocks in data from the Slave (Only uses MISO). You can even have a 3 wire variation where MOSI and MISO are tied together (half duplex only). It all depends on the type of spi device you are using. Additionally, SPI can do Full Duplex transfers, but not all devices support this. As Wikipedia states, most devices do half duplex, even when wired in 4-wire mode.

In that note, the SPI devices are write only.

As for the clock frequency question, there is no auto negotiation of clock speeds. This is decided while the master is being programmed. You have to account for it.

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  • \$\begingroup\$ Thanks! In this link in the Inside the box section, it is given that data are always transferred in both directions. What do they mean by that? \$\endgroup\$ – Gomu Feb 18 '13 at 5:00
  • \$\begingroup\$ @Gomu, just after that it explains, When the master generates a clock and selects a slave device, data may be transferred **in either or both** directions simultaneously. It also says that data is always sent in both directions, but this is a bit short sighted, and old (It's from 2002). SPI has no acknowledgement method, so data can be completely ignored, in either direction. And in reality, there is many one direction and half duplex SPI slaves. They don't all conform 100% to SPI, as seen in the Maxim app note. \$\endgroup\$ – Passerby Feb 18 '13 at 6:47
  • \$\begingroup\$ Yeah, I get it! And, could you please say the need for interrupt in master & slave? \$\endgroup\$ – Gomu Feb 18 '13 at 6:59
  • \$\begingroup\$ It's given in this link about interrupts in both master & slave. But, I couldn't understand it clearly. Can you kindly explain it? \$\endgroup\$ – Gomu Feb 18 '13 at 7:07
  • \$\begingroup\$ @Gomu, that's getting into the details of the AVR SPI peripheral and coding, which is not something I am too familiar with. That said, the SPIF is used to let you, the programmer/code know that the SPI peripheral is done sending/receiving the last transmission. The SPI peripheral is a hardware implementation of SPI, instead of a software implementation. It lets you set it up, give it some data, and it handles the data transferring in the background, so to speak. So the interrupt tells you when it is done. \$\endgroup\$ – Passerby Feb 18 '13 at 9:01
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In case of multiple slaves, does it mean, that it transfers data to many slaves, or it transfers data to one of the slaves, amidst a connection to many slave devices?

The SPI bus is a multi-tap bus for the "MOSI," "MISO," and "SCK" signals. Each separate slave has a separate "!SS" signal.

According to this link Figure 4, it is given that, the master keeps its SS low, until all the data it needs to send to the 3 slave devices is sent and then it makes the pin high. If so, what data & from which slave device, the master receives at the end? (As, I've learnt that, the master always receives something in return)

If a specific device doesn't affect the MISO pin, then multiple instances of that device on the same bus could receive the same data at the same time by keeping the !SS pin of each of those slaves low at the same time. This is not the common use of SPI. In the common use, a single slave is addressed at a time, and the master receives whatever that slave is clocking out while the master is clocking data into the slave.

As given in this link, in enhanced mode the load enable(LDEN) & WCOL is checked for moving next byte into the buffer. Why do we need to check them both? Isn't the WCOL sufficient for that?

This is specific to whatever device implementation you're talking about.

It's given that: "Master configures the clock - frequency less than or equal to the maximum frequency the slave device supports. Such frequencies are commonly in the range of 1–100 MHz." How does the master find the clock frequency of the slave?

Each slave may have a different limit on the upper speed of clock it supports. Each master may have a different limit on what clocks it can generate. It's up to the designer of the circuit, and the programmer of the master device, to select devices that will work together, and configure the clock frequency to work.

Does the SPSR, SPCR and SPDR registers remain in both master and slave?

That is specific to the particular device you're asking about. Those sound like SPI control registers in the Atmega MCU (or someone who uses exactly the same register names.) Atmega MCUs with SPI hardware has those registers, and can be programmed to work in both master and slave mode. However, each separate SPI bus capable device may use a different actual implementation, as long as the signal protocol is adhered to.

It is given that, the SPIF flag is set after the completion of transmission. If the SPIE is also enabled, then interrupt is produced. Does the flags get set in both master and slave? Does the interrupt is produced in both master and slave? It's given in this link about interrupts in both master & slave. But, I couldn't understand it clearly.

Again, that flag is specific to the implementation of SPI in a particular device; in this case seemingly an Atmega CPU. If an Atmega CPU is running SPI in slave mode, yes, it will raise the SPIF interrupt when receiving a byte in slave mode.

What is the application-oriented difference between the normal mode & enhanced mode? Both seem to wait for data to send/receive. What's the main difference?

That depends on what "enhanced mode" you're talking about, and would be specific to that particular device.

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