I was going through an article related to SPI. There was a configuration named 'Daisy Chaining', in case of multiple slaves. So far, what I have understood about SPI (based on Wikipedia) is:
SPI can transfer and receive some data simultaneously.
My questions are:
In case of multiple slaves, does it mean, that it transfers data to many slaves, or it transfers data to one of the slaves, amidst a connection to many slave devices?
According to Application note 3947, Daisy-Chaining SPI Devices, figure 4, it is given that, the master keeps its SS low, until all the data it needs to send to the three slave devices is sent and then it makes the pin high. If so, what data & from which slave device, does the master receive at the end? (As, I've learnt that, the master always receive something in return.)
As stated in Architecture and programming of 8051 MCU's, in enhanced mode the load enable (LDEN) & WCOL is checked for moving the next byte into the buffer. Why do we need to check them both? Isn't the WCOL sufficient for that?
It's states: "Master configures the clock - frequency less than or equal to the maximum frequency the slave device supports. Such frequencies are commonly in the range of 1–100 MHz." How does the master find the clock frequency of the slave?
Does the SPSR, SPCR and SPDR registers remain in both master and slave?
It is given that, the SPIF flag is set after the completion of transmission. If the SPIE is also enabled, then an interrupt is produced. Does the flags get set in both master and slave? Is the interrupt produced in both master and slave? It's stated in AVR151: Setup And Use of The SPI about interrupts in both master and slave. But, I couldn't understand it clearly.
What is the application-oriented difference between the normal mode and enhanced mode? Both seem to wait for data to send/receive. What's the main difference?