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I am designing a simple inrush current limiting circuit with a P-Channel MOSFET:

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The simulation shows a 48V source that switching on with a fairly fast rise time of 1ns. The Drain-Gate capacitor Cinrush shall cause the MOSFET to slowly turn on. However, during the 1ns rise time of the source, the current shows an extreme value of 1kA.

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What is causing this high current peak?

EDIT: Also is my understanding for this circuit correct: When first switching the source on, it is only limited by R1. Then Cinrush will be charged up to VG, which is defined over the voltage divider R1 & R2. The time constant is R1*Cinrush (neglecting all parasitic)?

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  • \$\begingroup\$ Add some practical impedance (series resistance) to the voltage source. \$\endgroup\$
    – jay
    Aug 26, 2021 at 15:29

2 Answers 2

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A typical MOSFET model has D-S capacitance and G-S capacitance and only tiny amounts of series inductance (mostly due to the package).

By feeding it a 1ns rise time input you are seeing the effect of those parasitic elements. They do exist in reality.

If the 1ns (or even 10ns) rise time is possible in reality you may wish to add some series impedance to limit the current if such elements (lumped or due to trace and wiring impedance etc.) do not already exist.

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Initially, VS=VD=VG=0. When you suddenly apply 48V to VS, VD and VG are both 0. That instantly turns on X2. X1 will quickly pull the gate up to 48-Vz, but only when Cinrush charges slightly and its charge plus VD takes VG up to VS-Vg,th will the inrush limiting start working.

Figure the ratio between 48V and Vg,th and add a cap from source to gate that much higher than Cinrush to yank the gate up with the applied power. For instance, if your minimum gate threshold is 1V, make that gate-source cap 4800pF or more.

Your circuit as is works well if you're applying power by turning the FET on with 48V already applied, but needs the additional cap to work when the 48V is switched on externally.

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  • \$\begingroup\$ yes but even then the peak appears as the instantaneous current is shorted to ground over all capacitors only limited by the source impedance (which i have not put in the simulation yet). \$\endgroup\$ Aug 26, 2021 at 15:36
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    \$\begingroup\$ Yeah, the three caps provide a path to ground, but that path is around 100nF in real life (maybe a bit more if you take into account the parasitics). If even that much inrush is too much for you, try putting a resistor in series with Cinrush. \$\endgroup\$ Aug 26, 2021 at 15:40
  • \$\begingroup\$ okay and with adding a cap from S to G will cause the initial voltage the gate "sees" to be 48V and X2 is off. Only after charging up the added S to G cap, the FET will turn on. But why do I need Cinrush still? \$\endgroup\$ Aug 26, 2021 at 15:54
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    \$\begingroup\$ With only Csg, charging the cap keeps it off until the gate threshold is reached, at which point it quickly turns full on. Cinrush, on the other hand, continues to provide negative feedback, raising the gate voltage as VD rises--essentially becoming a slew rate controller for VD. Only after VD ~= VS does X2 turn full on. It's not exactly a constant current controller, because the amount of inrush current allowed changes depending on Cin. \$\endgroup\$ Aug 26, 2021 at 19:16
  • \$\begingroup\$ And is there a simple way on how to calculate the time from threshold until the FET fully open? I have done some simulations and research but since it heavily depends on the MOSFET parameters, it can't just be easily calculated. \$\endgroup\$ Aug 28, 2021 at 5:42

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