I am trying to design a PLL using the ADF4XX series PLL from Analog Devices. I am taking design references from the EVM schematic.

I will be providing 10MHz reference and generating 40MHz using CVSS-945

In the EVM they have used ADCK92XX high-speed clock buffers at the Input and REFIN stage.

1.To maintain low phase noise at low reference and RF frequencies.

2.Designed specifically to minimize the added random jitter over a wide input slew rate

3.REFIN (10MHz) must meet the 50V/usec slew rate of the ADF4106; So ADCLK9XX was chosen to increase the slew rate of the 10MHz source.

4.They make sure that the additive jitter introduced by the REFIN is minimal.

5.The ADCLK9XX provides 50 Ohm termination at the input.

I have the following questions/doubts:-

  • Can I use another mechanism at the Input and REFIN, like Balun as in the below reference enter image description here

Because the clock buffer chip package is difficult for in-house soldering.


1 Answer 1


The issue you have is to ensure adequate slew rate at the reference input whilst meeting the limitations on the reference amplitude.

The CVSS-945 provides a minimum of 5dBm into 50 ohms at 10MHz, this is 560mV pk (1.12Vpk-pk).

For a sine wave:

\$v = A \sin (\omega t)\$

\$dv/dt = \omega A \cos(\omega t)\$

so the slew rate at the zero crossings is \$\omega A\$

For a 10MHz sine wave of amplitude 560mV, the slew rate is 35.2V/us. This is less than the 50V/us specified, and so is likely to degrade somewhat the chip phase noise FOM. This will degrade the phase noise within the PLL loop bandwidth. Whether or not this is adequate for your application is up to you.

Note that the typical CVSS-945 output of 7dBm gives a slew rate of 44V/us, much closer.

How to improve it without the buffer? Increase the amplitude of the signal at the ref input. The transformer you show seems to be 1:1, and if that is the case it won't achieve anything.

The input impedance of the ref input is high, so you could use a transformer with about a 1.4:1 turns ratio. You could go up to 2:1, but be careful that a high output osc doesn't overdrive the chip. Alternatively a simple LC match to a 100 ohms resistor across the ref input would also work. (5dBm into 100 ohms is about 800mV pk and about 50V/us).

Alternatively use a square wave source, or the low jitter buffers ADI recommend

  • \$\begingroup\$ Can I use LC matching to 100 ohms resistor across REFIN(pin 8) and REFINA (pin6) to achieve the required slew rate? \$\endgroup\$ Aug 27, 2021 at 11:22
  • 1
    \$\begingroup\$ The REFIN (Pin 8) is unbalanced, you drive it wrt DGND (Pin 9). If you match your osc output to a 100 ohm grounded resistor that you AC couple to REFIN then you are probably fine. If there are any problems they will show up as slight degradation of the in-band phase noise - and if this was critical to your application, and you had to get it right first time, then I'd drive the REFIN from a low impedance source with adequate slew rate. \$\endgroup\$
    – Tesla23
    Aug 27, 2021 at 22:46

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