I am trying to design a PLL using the ADF4XX series PLL from Analog Devices. I am taking design references from the EVM schematic.
I will be providing 10MHz reference and generating 40MHz using CVSS-945
In the EVM they have used ADCK92XX high-speed clock buffers at the Input and REFIN stage.
1.To maintain low phase noise at low reference and RF frequencies.
2.Designed specifically to minimize the added random jitter over a wide input slew rate
3.REFIN (10MHz) must meet the 50V/usec slew rate of the ADF4106; So ADCLK9XX was chosen to increase the slew rate of the 10MHz source.
4.They make sure that the additive jitter introduced by the REFIN is minimal.
5.The ADCLK9XX provides 50 Ohm termination at the input.
I have the following questions/doubts:-
Because the clock buffer chip package is difficult for in-house soldering.