Adjustable voltage, 1 MHz capacitive biasing

Question

I'm a budding physicist with little electronic design experience and am interested in driving an alternating E-field of adjustable strength within capacitive loads.

Buying a several thousand dollar piece of bench equipment to drive the devices I'm testing isn't in the cards so I've been trying to create a design to interface with my lab's function generator and power supplies.

Shown below is my initial design which has much more power draw than seems necessary.

The specs for my capacitive driver are

• Drive loads around 10k-100 kΩ, 10 n - 10 uF (100 kΩ, 10uF most importantly)
• Minimal current drawn through load devices
• 1 MHz switching (adjustable if possible... would be interested in also exploring some range of ~100 kHz - 10 MHz)
• ~20 - 100 V adjustable peak to peak output swings

Any advice on alternative designs or mitigations to the high power requirements of my current design would be greatly appreciated.

Answer 1

Your load current is 100kOhm not 10uF with a 1 s Vdc/ 2 time constant. Rise Times depend on R1 , fall times are driver RdsOn dependent.. both with Zo//cable capacitance only. Tr= 0.1us= 100R * C so Cout = 1 nF, Fall time is about 30 to 50 x faster so RdsOn is smaller than 100R by same.

Whenever a driver is design, you must have limits for Tr,Tf, Imax, Vmax and Z(f) for non-linear effects then compute Pd/Pmax < 50% unless a big heatsink is used or forced air cooling.

So start over with these requirements rather than just saying C, V,f ranges without mentioning the series R and ESR values of C.

If you need a PWM 100V motor/Piezo driver that's a off-topic shopping question, but you need help with the specs for impedance and power, so define the load as best as you can with links or specs.

If I guessed correctly, this may help your question. https://blog.piezo.com/how-to-drive-piezoelectric-actuators

Power Limits drive up the cost with 1kV/us switching speeds. But full bridge Silicon Carbide LC resonators may fit the low $/W requirement as a crystal oscillator.

Answer 2

Shown below is my initial design which has much more power draw than seems necessary.

That's because you are wasting most of the power in pullup resistor R1. You need a low value to reduce rise time, but when the FET is on the resistor uselessly draws 100 W continuously. With a 50% duty cycle the average power dissipation in the resistor will be at least 50 W.

To improve efficiency you could make a push-pull circuit with two FETs, one pulling down and the other pulling up alternately. The theoretical circuit looks like this:-

^{simulate this circuit – Schematic created using CircuitLab}

The drive waveforms must be 'complimentary' ie. when one is on the other is off. To prevent 'shoot-through' each waveform should be slightly more off than on (eg. 0.55 μs off and 0.45 μs) to ensure that each transistor has enough time to turn off before the other one turns on.

Even without shoot-through the pulse current during transitions can be very high as the Drain-Source and load capacitance is charged and discharged. To limit this current I added 50 Ω resistors in series. This should also protect the transistors from bad drive timing or a short-circuited output.

The upper FET's Gate drive has to be 'floating', as it goes up and down with the output. 'Half bridge' FET driver ICs are available which produce this floating Gate drive from a low voltage power supply, and also have a built-in delay or 'dead-band' to prevent shoot-through. However they are generally designed for with enhancement mode MOSFETs. You might consider using suitably rated MOSFETs instead of a rather exotic SIC JFET.