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I am designing a battery powered microcontroller circuit that will spend the vast majority of its life turned off. (In the absence of other recommendations, I'm thinking a few AA batteries in series followed by a linear voltage regulator is what I'm likely to use, but if there are other solutions that are better suited to this application, I'm all ears.)

A physical toggle switch will be used to turn the circuit on. As long as the switch is on, the circuit will 'do stuff.' The physical switch is a non-negotiable part of the design.

When the switch is turned off, the circuit will need another 2-3 seconds to finish its work, then should be powered off. It can then remain powered off for months at a time. I would like to maximize battery life by reducing/eliminating current draw when the circuit is inactive.

What kind of power solution can I use to meet these goals? I imagine that I'll use a GPIO on the microcontroller to signal, 'hey, I still need power,' and will need some kind of 'logical-OR' power control that will power the microcontroller when either the switch or the GPIO pin is active.

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schematic

simulate this circuit – Schematic created using CircuitLab

When the switch is in OFF position and PMS not conducting, the 100k resistor keeps the PMOS in non-conducting mode.

When the switch is ON position the MCU starts and it drives GPIO ON High, pulls the 100k resistor low and brings the PMOS into a conducting mode, so that the PMOS bypasses the switch. When the switch is turned off the GPIO detect signal goes low, so you can then power the PMOSFET off and the system as well

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    \$\begingroup\$ The second circuit's "GPIO On" has a leakage path when the power is off. \$\endgroup\$ Aug 28, 2021 at 17:12
  • \$\begingroup\$ @hacktastical where and how much did you estimate? \$\endgroup\$ Aug 28, 2021 at 17:23
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    \$\begingroup\$ Via R1 and the GPIO pin. There is a protection diode in the MCU that will leak current to the MCU’s VCC. Further, even if the GPIO is ‘true’ open drain (unlikely), it is being subjected, in theory, to 9V. Not good. What will actually happen is that the pin will bias to VCC + 0.7V or so, and the P-FET will always be on as a result. \$\endgroup\$ Aug 28, 2021 at 19:22
  • \$\begingroup\$ @hacktastical You are correct, I missed that, so I deleted the 2nd circuit. Thank you for your criticism. \$\endgroup\$ Aug 28, 2021 at 19:43
  • \$\begingroup\$ OK, so R3/R4 form a voltage divider and I choose values to ensure voltage on GPIO detect doesn't exceed Vcc. I can see that. What properties do I look for when selecting PMOS, D1 and Q1? I'm quite the dummy when it comes to analog electronics. Oh: and thank you! I appreciate the help! \$\endgroup\$
    – Nevo
    Aug 28, 2021 at 21:35
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This came up recently: How can I make this "automatic turn off" work using some GPIO pins on a MCU?

This circuit has the additional feature that it latches on, so that switch bounce won’t be a problem at turn-on before the MCU has had a chance to configure the GPIO. It can also use any kind of switch without regard to the current draw, so a membrane or carbon puck type can work. Finally, it could be modified to control an EN pin for a regulator instead of a FET.

Try it here

enter image description here

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