Switch-on time of an active p-channel MOSFET current limiting circuit

Question

I have recently posted a question on the design of an inrush-current limiting circuit:

Current limiting circuit with P-Channel MOSFET

I have decided to post a new question on how to analytically calculate the actual MOSFET opening time when adding an external capacitor C2, which increases the Miller capacitance of the FET.

So the following circuit will limit the inrush current into capacitor Cin when hot plugging the power.

The circuit works as expected as can be seen from the following plot:

I am now trying to understand how exactly the inrush time - so the time from the FET starting to open when the gate reaches the threshold voltage until fully open - can be calculated.

Calculating the threshold voltage - which is about Vth=-1V - is easy at it is determined by the time constant of the C1*R1||R2 circuit. It however becomes tricky once the threshold voltage is reached. C2 provides negative feedback to the gate. In other words it increases the Miller capacitance and causes the FET to open more slowly. I figured this can be best modelled as a integrating OP Amp:

Initially, the output voltage Vout is 0V and C2 is charged to Vin, which is 48V. C2 discharges over R2 to Gnd and once the Threshold Voltage Vth is it, the output voltage rises slowly. However, how do I bring R1 and C1 into play to match the timing of the voltage rise?

How can the actual inrush time be calculated?

EDIT 1

Based on jonk's answer below, the switch-on time can be estimated by the discharging current of \$C_2\$ and \$C_2\$ over the voltage divider network \$R_1\$ and \$R_2\$. The answer has the details in it and I will not cover them in this edit.

I also built a breadboard to compare the simulation results with the real-word circuit. I have to note that the initially selected MOSFET SI7465DP was not available, so I selected the slightly larger IRF9Z34PB P-Channel FET. I also measured all ceramic capacitors that I used for the breadboard and put the exact values into the simulation model. Firstly, here are the updated simulation results:

The linear region is about 2.3 ms:

The following photo shows the breadboard circuit:

And here are the measurement results with a linear region of 3.4 ms:

The threshold voltage is at around 2.6 V:

As can be seen, in the real circuit the linear time is about 3.4 ms, which is more than one ms longer than the simulation. What is causing this mismatch?

Answer 1

I think we both see things similarly, without the use of \$C_2\$. So that's a great base upon which I can attempt an answer.

To begin, though, I'd like to simplify your schematic. It will help a lot and it's my hope you will agree with the simplifications I'll make here:

^{simulate this circuit – Schematic created using CircuitLab}

(My apologies for renaming \$C_{in}\$ to \$C_3\$. I hope you won't mind.)

Cutoff Phase

Initially, \$C_1\$ charges via \$R_{\text{TH}}\$, driving \$V_{_\text{G}}\$ towards \$V_{\text{TH}}\$ (which must have been designed through the values of the resistor divider, \$R_1\$ and \$R_2\$, be lower than the threshold voltage of the FET, for obvious reasons.) We both agree that the RC time constant formed by \$\tau=C_1\cdot R_{\text{TH}}\$, combined with the FET's threshold voltage, is key in determining how long this initial phase takes and that something new happens, once the threshold voltage is reached.

So, up to this point, I think we both see very similarly. \$C_3\$ holds the drain voltage close to ground. And, of course, holds that shared end of \$C_2\$ close to ground, as well. \$C_2\$ is relatively small, compared to \$C_1\$. So as \$C_1\$ charges via \$R_{\text{TH}}\$ a small current is stolen from \$C_1\$'s charging in order to allow \$C_2\$ to follow the charging process of \$C_1\$. This stolen current will slightly alter the time that would otherwise be computed using \$\tau\$. But not by a lot. And at the end of this process, before something new happens, \$C_2\$ will charged to approximately \$V_{_\text{CC}}\$, less the threshold voltage of the FET.

Now, we come to that something new part.

Ohmic Phase

Once the FET moves out of its cutoff region, it moves into its linear/Ohmic region. Without \$C_2\$, this would be a rather shorter period of time. But with \$C_2\$ in place, this period is dragged out.

As the voltage on \$C_3\$ rises, it drives the other end (gate-side) of \$C_2\$ also upward. This acts in a way to drive the FET gate back towards cutoff, again. Now, it won't succeed in completely doing so, as there is a path for \$C_2\$ to continue discharging. But it will be held right at the brink.

So for a period of time, \$C_2\$ slowly discharges and slowly allows the voltage on \$C_3\$ to increase along a controlled ramp. Eventually, \$C_3\$ reaches the output voltage and \$C_2\$ no longer constrains the FET in its sub-threshold region. At this point, the whole process of this phase ends, as \$C_2\$ has been charged to exactly the threshold voltage of the FET (which has the opposite sign to when this process started) and the circuit enters the next phase, with the gate of the FET slowly declining towards \$V_{\text{TH}}\$ along the same curve it otherwise would have followed had \$C_2\$ not been present.

All \$C_2\$ does here is create a plateau where the FET operates sub-threshold.

Let's look at a simplified schematic for this phase:

^{simulate this circuit}

Note that during this phase, the gate voltage remains essentially fixed. It does not change. Again, the reason is simply that any changes at the output voltage caused by a trickle from the FET is immediately applied as a negative feedback to the gate voltage forcing the FET to move back towards cutoff. So the gate voltage during this phase can't really change much. It's stuck.

This leaves the primary discharging current for \$C_2\$ as \$\mid \:I_{discharge}\mid \:=\:\frac{V_{_\text{CC}}-\mid V_{_\text{TO}}\mid-V_{_\text{TH}}}{R_{_\text{TH}}}\$. All of this current goes to \$C_2\$ and not \$C_1\$, since the voltage across \$C_1\$ isn't changing.

In your case, this current is \$\mid \:I_{discharge}\mid \:=\:\frac{48\:\text{V}-1.4\:\text{V}-39.7\:\text{V}}{20.7\:\text{k}\Omega}\approx 330\:\mu\text{A}\$.

You need to completely discharge and then recharge \$C_2\$ over the entire \$48\:\text{V}\$ range. So you can compute the time required as \$t=\frac{10\:\text{nF}\:\cdot\: 48\:\text{V}}{330\:\mu\text{A}}\approx 1.5\:\text{ms}\$.

(Once this phase ends and \$C_2\$'s discharge/recharge process is over, the gate voltage can once again continue towards \$V_{_\text{TH}}\$ per the prior \$\tau\$ curve until it reaches \$V_{_\text{TH}}\$.)

You can easily adjust this time period by altering the value of \$C_2\$.

Also note that, as this is a relatively fixed \$C_2\$ discharge/recharge current, the voltage across \$C_2\$ is a linear ramp and therefore the output voltage will follow that same linear ramp.

As you can see, an overly complicated view isn't required and a simplified approach can get credibly close to actual behavior. The time period doesn't (much) depend on FET characteristics, as \$C_2\$'s current in this phase is set by the circuit and much less so by the FET.

Afterwards

With the output now settled, \$C_2\$ now provides feedback to the gate. If the output starts to decline, \$C_2\$ will pull down on the gate encouraging more current from the FET to compensate. If the output starts to rise, \$C_2\$ will drive upward on the gate discouraging current from the FET. So \$C_2\$ impacts two important behaviors.

Summary

So, set \$\tau_{_1}=R_{_\text{TH}}\cdot C_1\$ and \$\tau_{_2}=R_{_\text{TH}}\cdot C_2\$ and then you can compute the time for the first phase as:

$$ t_{_\text{cutoff}}= -\tau_{_1}\cdot\ln\left(1-\frac{\mid V_{_\text{TO}}\mid}{V_{_\text{CC}}-V_{_\text{TH}}}\right) $$

and for the following phase as:

$$t_{_\text{linear}}=\tau_{_2}\cdot \frac{V_{_\text{CC}} }{V_{_\text{CC}}-\mid V_{_\text{TO}}\mid-V_{_\text{TH}}}$$

In your example, you'd find that \$t_{_\text{cutoff}}\approx 3.8\:\text{ms}\$ and \$t_{_\text{linear}}\approx 1.4\:\text{ms}\$.

(Note that none of this includes your series resistor, \$R_5\$. But at \$1\:\text{k}\Omega\$ and \$330\:\mu\text{A}\$ the voltage drop is \$330\:\text{mV}\$ and I don't see how it significantly impacts the current or the timing. You should be able to vary that value somewhat without much impact.)

The most important aspect of this circuit isn't so much the timing of the cutoff phase (which is highly sensitive to specific FET parameter values and isn't so important) but is instead much more about the Ohmic region, which is where the output follows a controllable linear rise time. That's the main point of a circuit like this. And the prediction of that time should be fairly accurate using this simplified view.

Bear in mind that for these calculations, \$C_2\$ must be much larger than the FET capacitance. Otherwise, the error increases.

There is an additional time that continues \$\tau_{_1}\$'s decay, after \$t_{_\text{linear}}\$, but I'm not covering those final details here.

Anyway, I hope that helps.