The only reason I can think of for requiring symmetry in the gates' charging and discharging currents is that you require some corresponding symmetry in the rise and fall (sink/source) characteristics at the output side of the MOSFET(s).
In the schematic you provide, for example, R4 is responsible for pulling up the drain voltage of the MOSFET M1, which means the rising of the drain voltage is limited entirely by R4 and whatever load is connected there. But M1 is on the low side, able to yank its drain potential to 0V pretty much instantly. So, in such a design, I might legitimately infer that you are concerned with fall time at the output (ability to sink current), but not so much with rise time. In that case it's far more important for you to switch on M1 as fast as possible, but you don't really care how long it takes to switch off. That's a rather contrived reason why gate drive asymmetry may be acceptable, but it illustrates the point.
If the load (R4) in your circuit were inductive, like a relay coil, there's a good argument for switching on M1 quickly, but off as slowly as possible, to control back EMF and the associated RF mess.
I would say that in most power applications, including DC-DC converters, you require the fastest on/off transitions possible, and to heck with symmetry. Anything to compromise that speed, including any resistance from driver to gate, is going to slow things down, and heat things up. The goal for MOSFETS switching power is to obtain the largest excursions of, and fastest slewing gate voltage possible, without breaking anything.
That's not to say symmetry is never a concern. (This is another contrived example, but off the top of my head, it's the best I have) If you need a low impedance source of harmonically pure square output, you would endeavour to match rising and falling output transitions, necessitating a gate driver built with deliberate effort to compensate for things like NPN/PNP disparity, or overshoot and ringing. I would expect to find such measures (more complicated than you have implemented with R3, but in the same vein) employed at the gates of output MOSFETs in laboratory equipment, like function generators, partly in an effort to produce as symmetric an output as possible.
In response to A.H.Z's comment, on page 3 of this document the author states that to minimise "shoot-through" in a push-pull MOSFET pair, gate drive should be symmetrical. That's a somewhat sweeping statement, but it's not wrong, per se. This is referring to both voltage and time symmetry. Ideally you wish for one device to switch on at exactly the same time as the other switches off, which implies that each gate should be traversing its threshold at the same instant. This certainly implies temporal symmetry, but not necessarily voltage.
In the case of two MOSFETS whose gates are driven by the same signal, then you don't have much choice - I stick by my argument that the best medicine is to get that voltage from one extreme to the other as quickly as possible. If you have two MOSFETS whose gate threshold regions overlap somewhere between the supply rails, then that's marvellous, but the greater the difference in supply rail potentials, the less likely that is, the longer those two transistors will be conducting simultaneously, and every effort should be made to shorten that condition.
If however the gates are driven from separate voltage sources, timing becomes becomes a chief concern. If any delay causes one MOSFET to switch on before the other switches off, then you have problems. Having individual gate drivers for each transistor is really too complex a topic for a quick answer like this. A sweeping statement that "push-pull gate drive signals should be symmetrical" may be a good rule of thumb, but every application defines its own needs.