# How data is sent to a raw TFT?

I have used TFT drivers before but now I want to challenge myself by connecting an FPGA to a raw TFT without a driver.
I am having hard time understanding the basics of the signals : how RGB pins are clocked according to HSYNC and VSYNC pins ? After so much searching I think I am supposed to signal both HSYNC and VSYNC as start in (0,0) data and then to place each row’s dot RGB data with each clock pulse but can’t figure what I should do to H and VSYNC at each row / column change ?

• The detailed diagrams are on pages 8 and 9 - is there a specific question about them? Aug 29 '21 at 10:43
• I am supposed to signal both HSYNC and VSYNC ... that still involves the driver .... raw interface would involve driving rows and columns Aug 29 '21 at 17:32
• @Justme in page 7 seems VSYNC and HSYNC are active low while in page 8 they are active high. on the other hand I cant figure what I am supposed to do with DE . is it a separate mode or just need to be set high during the data transfer. same is ambiguous with ON_OFF , is screen on on 1 or 0 ? combination of me being a newbie and vague datasheet !
– Aug
Aug 29 '21 at 23:57

Vertical Sync or Frame Sync VSYNC defines the start and duration of a frame so one full picture, within this frame every column is initiated with the Horizontal Sync or Column Sync HSYNC.
So VSYNC is active for a whole frame and HSYNC is active for a whole column. Before both there's a backporch time, you should find these in the display's datasheet, during which the signal has to be low.