50% 555 cycle - comparing two diagrams

I'm getting started with an electronics project that's a bit more complicated than a simple pull-up and pull-down, using the 555. I've been reading up on it, and I think I understand how it works, but ran into two different designs for a 50% 555 circuit.

These are both images for a 50% design, posted in the same "tutorial". They seem to be identical, apart from R1 in image A, which is missing in image B. The description of this resistor:

Resistor R1 is used to ensure that the capacitor charges up fully to the same value as the supply voltage.

This description does not make any sense to me, as from what I understand the output switches to 0 when the threshold reaches above 2/3rds of VCC. This causes a path from C1 through R2 to 0v, which means C1 starts discharging. It therefore never reaches the supply voltage.

What would be a valid reason for implementing R1?

And a small unrelated question, can I use any capacitor >100nF for pin 5, e.g. 0.1F? I understand this could cause some "undefined" behavior for a couple milliseconds when powering up, but I don't care about that.

• What may not be mentioned: Using pin 3 in the timing loop may not be a good idea if pin 3 also drives significant current to a load. If output current changes the swing of output voltage from pin 3, then output frequency will change. The other astable circuit using pin 7 (reset) to discharge the timing capacitor through a resistor - is more frequency-stable when you load down pin 3. Aug 29 at 14:28
• @glen_geek Thanks for mentioning it. I'm simply using it to switch a mosfet, so shouldn't be a problem. And I just need to get close to 50%, not necessarily exactly 50%. Still good to know for future projects. Aug 29 at 14:32

Resistor R1 is used to ensure that the capacitor charges up fully to the same value as the supply voltage.

That's actually a nonsense reason because it's not true. As soon as the voltage at pin 6 (threshold) exceeds 2/3 Vcc then the output (pin 3) will change to a low state. So the 555 doesn't even allow C to be charged to the supply voltage!

The only thing I can see that R1 does is that it influences the charging/discharging of C1 such that the duty cycle is not 50 %.

If you want 50% dusty cycle, use the circuit without that R1.

Try it on a breadboard and see what happens!

And yes, using a 100 nF capacitor for C is perfectly fine.

• Perhaps R1 is important if you have a variant of the 555 where pin 3 is open-collector? (I'm not sure if that is a chip that actually exists) Aug 30 at 9:12
• @user253751 I am unaware of such a version, perhaps you are thinking of the discharge output (pin 7) which is an open collector. If the output was open collector it would be hard to get 50% duty cycle same as in the default 555 configuration. Aug 30 at 11:32

R1 is redundant , and possibly an error adding it does nothing much except shift the average DC level of a triangle waveform and thus the duty cycle.

If you desired to null the error of the average 1/3 2/3 thresholds compared to the average swing of the output, you could use a pull up or down to offset the duty cycle or null it to 50% with say -60 dB 2nd harmonic content.

Large C's also have large leakage current. This creates an equivalent resistance, and decay time Rp*C=T affects the maximum charge time constant. If you had 2 of them, you could try to equalize the leakage, and then you have twice the leakage. But at least a symmetrical duty cycle but now the series R and leakage R cause attenuation in the feedback, so if it cannot reach V/3 or 2/3V then it stops oscillating.

If you want really long time constants or really low f, use a CD4060 instead ;) You can make a clock with 14 stage divider FF's.

• Although I feel like this answer contains more information, I accepted the other answer. This since I indicated being a relative beginner, so "-60 dB 2nd harmonic content" means nothing to me without diving into another hour long research ;) The CD4060 is a good suggestion, but I think for my current project a bit of an overkill. Aug 29 at 14:30
• Square waves have no even harmonics unless asymmetrical. so -60 dB means 0.1% error on symmetry. I would have thought 0.1 F was overkill ;) Any CMOS Schmitt inverter can do this easier. You do not ever need to use a 555. Aug 29 at 14:53

R1 corrects partially for the asymmetry of the bipolar 555.

The CMOS 555 is also assymetric but not as bad as the bipolar.

how close do 50% do you need?

I am surprised at the responses from Bimpel and Tony. I think Bimpel is incorrect, while Jansen got it right. As for Tony's response, he starts out saying R1 is redundant and possibly an error, and then the rest of that same sentence says exactly why R1 is needed.

I agree that one of the reasons given for the added resistor, that it pulls the capacitor voltage up to Vcc or closer to Vcc, is wrong. However, the resistor does compensate for a characteristic of the bipolar 555 output stage, and improves the circuit performance.

The standard 555 equations assume that the output swings between 0.000% of Vcc (GND) and 100.000% of Vcc. In real life, both assumptions are wrong. While the CMOS version is better than the bipolar version, both types have an output that is not perfect; the high output (Vhi) is some number of volts less than Vcc, and the low output (Vlo) is some different number of tenths of a volt above GND. Again, the CMOS part is much better, so this discussion primarily is about the bipolar part.

While it is true that the timing capacitor voltage oscillates between 1/3 and 2/3 Vcc, and never approaches either rail, that is not the point. The point is that the charging/discharging currents are dependent on the voltages across the timing resistor. These are the voltage difference between 2/3 Vcc and Vlo, and the difference between 1/3 Vcc and Vhi. Because the 555 high and low output voltages are not symmetrical in their distances from their respective rails, the charging and discharging currents are not equal. Thus, the circuit does not produce a 50/50 square wave.

The CMOS 555 is much better at this, as its output headrooms or margins are very close to equal. But the bipolar 555 is worse. As above, Vhi can be over 2 volts below Vcc, while Vlo is around 0.5 V above GND. This is the reason for the added resistor from the timing capacitor directly to Vcc - it pees in a small current so that the total charging current is closer to the discharge current. This makes the output duty cycle closer to 50/50.

There is no way to calculate an exact value for the added resistor, because the output stage headroom requirements change with output load current, with temperature, and from part to part due to process variations. An approximate value or starting point can be determined using the parameters in the datasheet.

Using the resistor from pin 3 (output) is best done with a CMOS 555 and with minimal loading on the output. If you have to use a 555 at all.

The old bipolar versions have an output swing (even under minimal loading) that will go from near 0V (zero sink current) to a volt or more below the supply voltage (zero source current). You can fiddle the duty cycle as shown but (with the bipolar type) it will vary with timing resistor and power supply voltage. Lightly loaded, the output of the CMOS type will swing to within mV of the supply rails and any difference is essentially resistive, not a fixed voltage drop (however the resistance is asymmetric).

If you need very close to 50%, it's better to ensure the supply voltage is stabilized and feed the output to a flip-flop. You can then use the conventional circuit with the discharge output. Even with a flip-flop if the supply voltage dips when the output turns on or off you can get asymmetry. A very high frequency divided down can further reduce that effect even if the supply voltage dips down a bit since the 555 thresholds are ratiometric with supply voltage.

The bypass capacitor on the control voltage input is looking into a Thevenin equivalent impedance of 5K||10K on bipolar LM555/NE555 and more like 100K||200K on something like the LMC555 CMOS version. The resistances are not well controlled and vary with temperature and supply voltage, but that's roughly what they are.

So the time constant $$\\tau\$$ will be < 20ms for C < 6uF in the first case and for C < 300nF in the latter (meaning virtually all effects will be gone in $$\5\tau\$$ or 100ms). So 0.1uF (100nF) ceramic is fine.

A 100uF electrolytic used with a CMOS 555 would have a time constant of 6.7 seconds so the duty cycle would be affected for something like half a minute, and leakage could also cause it to remain off a bit.