# Loop filter bandwidth calculation

I am trying to Design a PLL using ADF4106 and VCXO. The reference frequency is 10MHz and VCXO output is 40MHz.

I need to design a Loop filter for converting charge-pump voltage from PLL into Control Voltage VC for VCXO.

I found this document which shows the calculation of R, C and Loop bandwidth of the Loop filter.

I need the following parameters for Loop bandwidth calculation.

I need to calculate natural frequency "fn" for calculating bandwidth.

Natural frequency can be calculated by the following formula.

I need help in calculating Fn to determine the loop bandwidth.

• You need to define your expectations for capture time, Noise BW,, phase noise or whatever Aug 31, 2021 at 5:23
• If you see a circuit diagram of a completed PLL, you can analyse what the fn is by calculation from the RC values. However, you need to synthesise a loop, which means choose an fn for your purposes, then derviing RC values. What are the constraints in your application? Do you need lowest possible noise? Do you need capture or settling faster than some time? Do you just want something that's stable and the right frequency, and you'll refine noise and speed later if you need to? Hint, bandwidth need have nothing to do with the loop filter, it's easier than the 4106 sheet suggests. Aug 31, 2021 at 5:40
• Have a look at this answer of mine, where I break down what a PLL and loop filter are, and do a worked example, albeit for a different part number PLL (also Analog Devices, so should relate easily) Aug 31, 2021 at 7:46

To design PLLs with the ADF4106 it's easier to use ADIsimPLL:

If you want to do it yourself, try: NI AN1001

if your application is non-critical, good starting values are the loop bandwidth at up to 10% of the phase detector frequency and around 45-50 deg phase margin.

Just noticed you are using a VCXO - you will probably want a narrow-band loop.

• This method of shoot then aim after is not recommended. Pls write or wait for specs first Aug 31, 2021 at 5:58
• If you are designing with one of the free tools like ADIsimPLL for the ADF4106, you can just choose a starting LBW and phase margin, observe the achieved phase noise, jitter and lock times, and manipulate the bandwidth and phase margin to get the performance you want. Unless you really know what you are doing, (in which case you wouldn't be asking here) starting with a loop bandwidth up to 10% of the phase detector frequency and 45-50 deg of phase margin is good advice. Aug 31, 2021 at 11:08
• Yes but a 10MHz Ref and a Low-phase noise sinusoidal VCXO with a 20 PPM error max with a PLL using a type II mixer begs some questions. Anything will work but is complete overkill with the PD phase noise. Aug 31, 2021 at 12:37
• Also you can use many free tools on almost any PLL. Aug 31, 2021 at 13:01
• Yes, but a personal observation is that the ADI tools work well for ADI chips and the TI tools work well for the TI chips etc... Aug 31, 2021 at 20:53

This combination of VCXO and PLL is complete overkill when you can accomplish the same with a single $5 CD74HC297 PLL chip with both mixer types XOR and Edge Phase/Freq. The filter is usually a 10C//RC to get phase lead compensation at unity gain for a more damped response and slew rate is your choice except XOR needs to see the mixer output with low phase shift to achieve better phase margin at DC yet filter the max 2f error to correct the VCO slowly on each cycle without 40MHz ripple. • so using 10% of the mixer BW as a starting point is overkill but works with lose on the XOR and overkill for the edge type. XOR has lower phase noise but needs at least 3 times the bandwidth of the initial max frequency error to capture as the mixer produces 2f output to the LPF integrator. It has many counters insider. So you even could produce 40MHz from 1MHz or 100 Hz. The edge mixer will capture any frequency error and slew rate of filter determines lockup time. But the edge noise creates much phase noise, which is why the "Suggested low noise VCXO " is overkill. If you wanted the best of both compromises , fast lockup time and low phase noise, you would use the lock detector to switch bandwidths and/or mixers (aka phase detectors (PD). • We don't know the OP requirements, hence we should be careful describing a solution as overkill. What's wrong with one 40MHz osc and a divide by 4? I don't know - but they may. A PLL using a vintage CMOS phase detector may be a reasonable solution, but if phase noise is an issue then a modern PLL chip like the ADF4106 with a FOM of -223dBc/Hz (approx 1ps timing jitter) will be far better. A phase/frequency detector means you don't have to worry about capture range and the balanced charge pump minimizes reference sidebands. They may have found the ADF4106 is around$5 too. YMMV Aug 31, 2021 at 20:52