Say I have module_A , module_B and module_C and a variable as “reg[3:0] x”. I want all three modules A,B and C have access to read and modify variable x ( something like global variables ). Is it possible to have such variable in Verilog ( Specifically Vivado ) ?

  • 4
    \$\begingroup\$ Any reason for you to not just have a signal 'x' connected to each of those three modules? Verilog is not that much like programming languages, you are describing hardware. And having some module depend on some "global" thing that is connected to who knows how many other modules seems like a bad practice, and probably not synthesizable. \$\endgroup\$
    – jDAQ
    Sep 1, 2021 at 4:44
  • \$\begingroup\$ You may need to provide some context on why you concluded this 'global variable' is a necessity in your design. Otherwise, this may look like XY problem. \$\endgroup\$
    – Mitu Raj
    Sep 1, 2021 at 8:21
  • \$\begingroup\$ A variable in Verilog becomes an electrical signal in the synthesized hardware. A signal cannot be driven (modified) by more than one module without some sort of protocol (logic) in place to determine which module is "in control" at any given moment. \$\endgroup\$
    – Dave Tweed
    Sep 1, 2021 at 10:59
  • 2
    \$\begingroup\$ Yes, 1) Create module_D that has "the global variables". 2) Wire modul_[A..C] to module_D. \$\endgroup\$
    – jay
    Sep 1, 2021 at 12:51
  • \$\begingroup\$ Note that even in an actual programming language (like C, as opposed to hardware description languages), having a global like that would be something that should not pass basic code review – it's a bad idea all around. I don't intend to be mean, but if your design requires something to be global, you've probably haven't designed it sensibly to avoid all kind of nasty situations, AND in digital design, you neglect the fact that you're actually dealing with things that have a propagation delay – not trying to keep state as local as possible has ruined the clockability of many a design. \$\endgroup\$ Sep 1, 2021 at 17:49

2 Answers 2


You are asking the wrong question.

In Verilog simulation, every signal can be a global. For debugging, we need to be able to see and potentially modify everything.

In Verilog synthesis, nothing is a global (except maybe power and ground signals handled as a special case). Every state variable needs a path/wire/port/interface to move its value from one place to another.

Typically a memory can be used as a group of addressable global variables and shared between modules. But you need some kind of protocol (like AMBA/PCI) that arbitrates access.


Verilog hierarchical dot notation might give you what you want. See https://www.chipverify.com/verilog/verilog-hierarchical-reference-scope.

Not everything in Verilog will need to be synthesizable. There are modules that will be models and those that will be testbench units. For example, a load of (RNM = real number modeling) models of analog blocks in a simulation might want to refer to the temperature. You'd want all the models of analog circuits to refer to that directly (through hierarchical dot notation) and most definitely not through a port that doesn't exist in the design.


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