# When input clock frequency out of range, provide alternative clock

I have a system that receives a ~352 MHz clock signal that is divided down to provide clock signals (that are phase synchronous with the 352 MHz master clock) to various modules. The precise frequency of the 352 MHz clock signal is important since it is used to set time delays (i.e., phase shifts) between the lower frequency clocks. Occasionally, there are periods of time in which the 352 MHz clock is either unstable or unavailable, causing the system as a whole to be inoperable. The 352 MHz clock is provided externally, so I do not have control over it to make any changes.

I would like to have something that sits between the 352 MHz clock and the frequency division hardware that detects when the clock is outside of some valid range and then switches the system to an alternative clock source that I provide. In essence, the system would have two operating modes: (1) phase locked to the external 352 MHz clock and (2) unlocked from the external clock but still operating at a precise 352 MHz frequency. My thought was that this could be done with a PLL that phase locks to the 352 MHz external clock. The PLL bandwidth could define the frequency range in which the output frequency will track the input frequency. When the input frequency deviates too far, the PLL would become unlocked and send a signal to switch in a different clock source. My main concern is that the valid frequency range might be quite narrow, perhaps as small as a few Hz. Is this a viable approach or is there a better method?

• You need to phase align your local backup oscillator to the external clock. Sep 1 '21 at 15:33
• Instead of the frequency, detect the phase, which is already available from the PLL. In order to detect 3Hz out of 352MHz, the detector has to count for 1 second and find 1 count difference, which is still not available due to that the PLL is going to be locked to the input.
– jay
Sep 1 '21 at 16:18
• Define the tolerance error of your system! 1ppb? 1ppm? Sep 1 '21 at 19:54
• @DKNguyen what stops ext. Clk from drifting? Nothing, until we get a spec on tolerance error. Sep 1 '21 at 19:56
• @TonyStewartEE75 I totally agree. It occurred to me as I was writing the question that it could be difficult to answer without better defining the allowable tolerance for the clock frequency, so I'm working on figuring that out. Sep 2 '21 at 13:37

This assumes you have a frequency reference for your local synthesiser that is synchronised to or superior to that used by the external 352 MHz. If your limit was (say) 3.5 Hz, that's 1 part in 108. Even a very good ovened crystal source could have ageing approaching 1 in 106 in a year. Unless you have access to the external frequency reference, you need to rethink your perhaps as small as a few Hz limits. As Dave Tweed has pointed out in comments, GPS disciplined references would fit the bill.