I have a system that receives a ~352 MHz clock signal that is divided down to provide clock signals (that are phase synchronous with the 352 MHz master clock) to various modules. The precise frequency of the 352 MHz clock signal is important since it is used to set time delays (i.e., phase shifts) between the lower frequency clocks. Occasionally, there are periods of time in which the 352 MHz clock is either unstable or unavailable, causing the system as a whole to be inoperable. The 352 MHz clock is provided externally, so I do not have control over it to make any changes.
I would like to have something that sits between the 352 MHz clock and the frequency division hardware that detects when the clock is outside of some valid range and then switches the system to an alternative clock source that I provide. In essence, the system would have two operating modes: (1) phase locked to the external 352 MHz clock and (2) unlocked from the external clock but still operating at a precise 352 MHz frequency. My thought was that this could be done with a PLL that phase locks to the 352 MHz external clock. The PLL bandwidth could define the frequency range in which the output frequency will track the input frequency. When the input frequency deviates too far, the PLL would become unlocked and send a signal to switch in a different clock source. My main concern is that the valid frequency range might be quite narrow, perhaps as small as a few Hz. Is this a viable approach or is there a better method?