# VHDL code not compiling

I'm new to VHDL and I cannot seem to get my code to compile. I've looked over the code to the best of my ability, but I do not see anything wrong with it from my current basic understanding of how it works and I am wondering if anybody could help. The code is supposed to model a NLX1G99 configurable multi-function gate (minus the enable bit)

library ieee;
use ieee.std_logic_1164.all;

entity multifun_gate is
port(
d,c,b,a: in std_logic;
y: out std_logic
);
end multifun_gate;

architecture dataflow of multifun_gate is
begin
y <= (a and not b and not c and not d) or
(a and b and not c and not d) or
(not a and b and c and not d) or
(a and b and c and not d) or
(not a and not b and not c and d) or
(not a and b and not c and d) or
(not a and not b and c and d) or
(and and not b and c and d);
end dataflow;

• What are the errors? – Dean Feb 19 '13 at 9:41
• This is a good example of total incomprehensible and undebugable code. Can't you write what you mean so that people can understand, and the synthesizer can create the gates? – Philippe Feb 19 '13 at 12:21

In the second last line:

(and and not b and c and d);

you have and repeated.

• Thanks, that got rid of one error, however, there are still others – audiFanatic Feb 19 '13 at 2:13
• nevermind, that did it. I meant to write "a and not b" rather than "and and not b" and I forgot to replace the and with a after fixing it. – audiFanatic Feb 19 '13 at 2:17

Judging from the picture in the datasheet, I'd write:

sig1 <= a and not c;
sig2 <= b and c;
sig3 <= sig1 or sig2;
y <= d xor sig3;


Much easier to check I reckon.

• I would've done that, but that's the way we were asked to do it. – audiFanatic Feb 25 '13 at 15:14
• @audiFanatic: ahh. Painful! I love it when people are "taught" to fight the tools :) – Martin Thompson Feb 25 '13 at 15:35