I'm new to VHDL and I cannot seem to get my code to compile. I've looked over the code to the best of my ability, but I do not see anything wrong with it from my current basic understanding of how it works and I am wondering if anybody could help. The code is supposed to model a NLX1G99 configurable multi-function gate (minus the enable bit)
library ieee;
use ieee.std_logic_1164.all;
entity multifun_gate is
port(
d,c,b,a: in std_logic;
y: out std_logic
);
end multifun_gate;
architecture dataflow of multifun_gate is
begin
y <= (a and not b and not c and not d) or
(a and b and not c and not d) or
(not a and b and c and not d) or
(a and b and c and not d) or
(not a and not b and not c and d) or
(not a and b and not c and d) or
(not a and not b and c and d) or
(and and not b and c and d);
end dataflow;