If you are within 1%, you should be OK.
Suppose your UART uses a 16x oversampling clock, for example, you can set it to 1,843,200 Hz to 16x oversample 115,200 bps. (oversampling like this is fairly common) This lets the UART count off 8 over-clocks from the falling edge of the start bit, so it can locate the center of the bit cells to within +/- one period of the over clock, after which it counts off 16 periods of the over-clock to determine when to sample data.
If you assume it can hit the center of the start bit, then in order to keep sampling serial data in the correct bit cells across 8 data bits, the clock frequency has to stay between (8-0.5)/8 and (8+0.5)/8, or +/-6.25% of the intended bit rate. Higher overclocking gets closer to the ideal condition of hitting the center of the start bit, but 8x or 16x is usually close enough that you can assume a 5% mismatch will work.
However, you can't count on the other side being perfectly on frequency. If you connect a device that's 4% fast to a device that's 4% slow, you'll have a problem. I've run into at least one case were a PC was running a little slow, and a device a little fast, and the two could only marginally communicate, though the same device was fine with other PCs, and the PC was fine with other devices. (O-scoped these at about 112kbps and 119kbps) For that reason it's good to try to hit the nominal frequency as closely as possible. I've never seen anything within 2% of nominal have a problem.
The usual thing to do is use a master clock rate that provides a whole number multiple of the intended UART over-sampling rate times the baud rate. For example, if you wanted a CPU running at about 8MHz, you might use a 7.3728MHz oscillator, which can be divided by 4 to get 1.8432MHz, which happens to be exactly 16 times 115200.