0
\$\begingroup\$

I am stydying the Quartus II + TimeQuest Analyzer. The documentation is abreast, the examples are not that of, and explanations for beginners are scarce.

Here's the simple code:

module test_project (
    input wire clock,
    input wire reset,
    output reg data = 1'b1
);

reg [1:0] div = {2{1'b0}};
always@(posedge clock)
    div[1:0] <= div[1:0] + 1'b1;

wire clk_enable = (div[1:0] == 2'b00);
    
always@(posedge clock or negedge reset) begin
    if(!reset) data <= 1'b1;
    else if(clk_enable)
                data <= ~data;
end

the contents of SDC file is:

create_clock -name {clock} -period 229MHz [get_ports {clock}]

Here's timing report from TimeQuest:

enter image description here

for the following path:

enter image description here

The above was generated using "report timing" custom report dialog.

I do not understand why it shows only one path (while there're more paths in the design), and why it does not see that there's clock enable of 4 clocks. Whatever I put into multicycle command into SDC file, I do not get what I think must see - the constraint that data from launching adder will reach output data register for latching within 4 cycles of the clock.

What is the logic of doing this simple constraint for this scenario (and why)?

If it will be properly constrained in the SDC file, will Quartus try to fit having this constraint fulfilled with no violations, right?

\$\endgroup\$
8
  • \$\begingroup\$ It should be showing the worst-case timing path cz that's the slack we should be worried about. See detailed report to see all timing paths. \$\endgroup\$
    – Mitu Raj
    Sep 2 at 14:59
  • \$\begingroup\$ Why you didn't add multi-path constraint on data path? \$\endgroup\$
    – Mitu Raj
    Sep 2 at 15:01
  • \$\begingroup\$ I think from my question is clear that: I am not able to understand "detailed report", and that I can not add proper pultipath constraint because I do not know how to do it. Can you give example to achieve the goal? And then explain it? \$\endgroup\$
    – FPGA lover
    Sep 2 at 15:34
  • \$\begingroup\$ You should check the Altera tool guide, to find how to see the detailed timing report. What you have been shown is just summary of timing with critical path only. \$\endgroup\$
    – Mitu Raj
    Sep 2 at 18:36
  • 1
    \$\begingroup\$ Did the answer solve your question? \$\endgroup\$
    – Mitu Raj
    Sep 3 at 18:02
2
\$\begingroup\$

Looks like your tool is showing only the critical path, i.e., the one with the worst slack. There must be specific command/option to see detailed timing report which shows all timing paths.

By the way, create_clock constraint sets up the basic clock constraint for Timing Analyser to synthesise and optimize the timing performance of the design. Since clk_enable has a time period of four times that of clock, and it enables data bus when it has to be driven, you can relax timing on its timing paths by taking advantage of multi-path timing constraints. For e.g., something like this:

set_multicycle_path -setup -end -to [get_registers data[*]] 4

set_multicycle_path -hold -end -to [get_registers data[*]] 3

This will multi-path constraint all timing paths to data registers with setup requirement = \$4\$ destination clock cycles and hold requirement = \$3\$ destination clock cycles. In this case, all of the filtered timing paths are reg-to-reg paths which are fed back from data bus.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.