0
\$\begingroup\$

enter image description here

Why RAS is still active when the column address is on the address bus?

I don't understand why RAS & CAS both should be active when column address in provided in address bus?

\$\endgroup\$
0
\$\begingroup\$

why RAS & CAS both should be active when column address in provided in address bus?

Not always. Often RAS, CAS, WE, and portion of the Address are encoded as "command"; like read, write, refresh, configurations, and etc. Otherwise, as the reason why you asked the question, RAS could just fulfill setup and hold time only.
An example is here.

\$\endgroup\$
0
\$\begingroup\$

RAS has other functions inside the DRAM besides latching the row address. It is the main control of the page cycle which triggers the fetch then write-back of the page. It needs to be held until the page access is finished. As DRAMs have evolved it has taken on other functions when encoded with the other control signals (CAS-before-RAS refresh for example.)

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.