DIP alternative to dual-port SRAM that doesn't require obsolete chips?

Question

I have a microcontroller "A" and 8-bit game console "B" that I'd like to be able to share a 2Kx8 SRAM address space. "A" will only write to RAM, and "B" will only read. A dual-port SRAM would handle this. However, the DIP dual-port SRAM I can find all seems to be obsolete (or out of stock and prohibitively expensive). I realize with DIP that obsolete is just a matter of time, and it seems like that time may have already come for DIP dual-port RAM. So, I'm looking for an alternative, if there is one.

Is there a way to accomplish this using as few 5V non-obsolete DIP IC's as possible? I'm hoping that the fact that there's no need to support R/W for both "A" and "B" provides an opportunity.

Some other limitations:

• I only have around 12 square inches (3"x4") of board space on one side. I suppose I could use the back too, but I'd have to be able to access the pins on the other side to solder them. So basically I'd only be able to overlap a smaller and larger IC. I also have limited vertical space, so I won't be able to stack boards or such, plus that sounds like an assembly nightmare.
• I have control over how "A" is wired and behaves, but "B"'s wiring and operation is fixed and is limited to reading from addresses spanning A0-A13 (so there are 3 spare address lines A11-A13 to work with, although they can only be set for around 300ns while reading a byte, they aren't GPIOs), and D0-D7 for data. I don't have access to "B"'s clock.
• I'm dead-set on using DIP, for aesthetic reasons (so I don't want to use SOIC adapter boards or such).

I considered hooking "B" directly to "A" with no SRAM in the middle, and serving up "A"'s internal SRAM to "B". By the numbers, I believe "A" is just barely fast enough to accomplish that. However, "B" will be reading pretty much constantly. Processor "A" wouldn't really have any clock cycles left over to be useful, so I scrapped that idea.

Another idea I had was to use two 2Kx8 SRAMs. Processor "A" could write to one of them while "B" read from the other. Then, when "A" was done writing to RAM, it could toggle an input to switch the roles of the two SRAMs. I based this on the concept of double-buffered graphics (and, indeed, Wikipedia even mentions it as an alternative to dual-port RAM: https://en.wikipedia.org/wiki/Multiple_buffering), so I feel like I'm on the right track. I think I could accomplish this with a bunch of quad bilateral switches (74x4066 or similar, 74x245 also seemed possibly useful), but for my application they waste pins and I'm not sure that I'd have enough space. I found an octal FET bus switch (74x3245) that seemed perfect, but it was obsolete.

When Googling, I saw someone mention using an SRAM twice as large so the writer would be in a different part of the RAM than the reader, but I feel like I'd still have address and data line contention with that approach, unless I'm missing something obvious.

Answer 1

The old trick is to get a very fast ram chip. The old 32kx8 cache rams should be plenty quick as they were better than 35ns usually. They’re also skinny dip. For the address mux you could use 74x157, 74x244 or 74x245. For the data bus mux, two 74x245. That’s the easy part, the tricky part is the logic that determines the start of cpu B’s bus cycle. From that point you know you have X time to sneak in, perform cpu A’s read or write then switch back with plenty of time to satisfy cpu B. If cpu B takes 300ns for a read, you’ve got plenty of time. Cpu A needs to be told to wait or implement a bit-bashed bus cycle that can be held off.

Thinking a little more, if you bit bash cpu A bus cycle, use 74x574 for the address latches. Cpu A can load the address it wants into the latches, set a request and the logic waits for a cpu B cycle then does its magic and flags when it is done. For the logic I’d use a GAL, but that might be counter to your retro leanings.

For a recent retro project, i just used a 600MHz microcontroller to sniff the bus and do the magic. Much simpler. Took about 60% of the cpu time though.

Best if I expand on the 'old method'- For point of reference, let's say cpu A is an AVR mega328. That micro is rather limited on port pins, so we need to be a little creative. Using 74x574 tristate D registers means we can create an 8 bit bus from the AVR and connect this to the two 74x574 and use them as an address latch - the AVR writes the low address to one, then the high address to the other. Then the AVR could present the write data to the 74x245 then set a flag to the magic logic to say we want to write. The logic would wait for the beginning of a bus cycle on cpu B, disable the 3state address buffers and data buffer from cpu B to the ram, then enable the address registers (these have the address already), then enable the data bus buffer for cpu A then perform a write cycle to the ram, say in less than 150ns. Once done, it disables the cpu B registers and buffer and enables the cpu A buffers. cpu A knows no difference.

Draw up a block diagram to get a clearer picture.

Then work on a timing diagram and incorporate the enable/disable times of the buffers etc, the setup and hold times of the ram.

From that you can formulate the logic and the timing required. How you ensure the timing be it through using a finite state machine or clocked logic or using gate and r/c delays is up to you.

The Apple II and many other computers of the day performed similar techniques to interleave the video accesses to memory with cpu access.