I have a microcontroller "A" and 8-bit game console "B" that I'd like to be able to share a 2Kx8 SRAM address space. "A" will only write to RAM, and "B" will only read. A dual-port SRAM would handle this. However, the DIP dual-port SRAM I can find all seems to be obsolete (or out of stock and prohibitively expensive). I realize with DIP that obsolete is just a matter of time, and it seems like that time may have already come for DIP dual-port RAM. So, I'm looking for an alternative, if there is one.
Is there a way to accomplish this using as few 5V non-obsolete DIP IC's as possible? I'm hoping that the fact that there's no need to support R/W for both "A" and "B" provides an opportunity.
Some other limitations:
- I only have around 12 square inches (3"x4") of board space on one side. I suppose I could use the back too, but I'd have to be able to access the pins on the other side to solder them. So basically I'd only be able to overlap a smaller and larger IC. I also have limited vertical space, so I won't be able to stack boards or such, plus that sounds like an assembly nightmare.
- I have control over how "A" is wired and behaves, but "B"'s wiring and operation is fixed and is limited to reading from addresses spanning A0-A13 (so there are 3 spare address lines A11-A13 to work with, although they can only be set for around 300ns while reading a byte, they aren't GPIOs), and D0-D7 for data. I don't have access to "B"'s clock.
- I'm dead-set on using DIP, for aesthetic reasons (so I don't want to use SOIC adapter boards or such).
I considered hooking "B" directly to "A" with no SRAM in the middle, and serving up "A"'s internal SRAM to "B". By the numbers, I believe "A" is just barely fast enough to accomplish that. However, "B" will be reading pretty much constantly. Processor "A" wouldn't really have any clock cycles left over to be useful, so I scrapped that idea.
Another idea I had was to use two 2Kx8 SRAMs. Processor "A" could write to one of them while "B" read from the other. Then, when "A" was done writing to RAM, it could toggle an input to switch the roles of the two SRAMs. I based this on the concept of double-buffered graphics (and, indeed, Wikipedia even mentions it as an alternative to dual-port RAM: https://en.wikipedia.org/wiki/Multiple_buffering), so I feel like I'm on the right track. I think I could accomplish this with a bunch of quad bilateral switches (74x4066 or similar, 74x245 also seemed possibly useful), but for my application they waste pins and I'm not sure that I'd have enough space. I found an octal FET bus switch (74x3245) that seemed perfect, but it was obsolete.
When Googling, I saw someone mention using an SRAM twice as large so the writer would be in a different part of the RAM than the reader, but I feel like I'd still have address and data line contention with that approach, unless I'm missing something obvious.