# Verilog Simulation: 16 to 1 Mux Output High Z

Verilog beginner here. I am attempting to implement a 16to1 mux by instantiating four 4to1 muxes. Here is my code:

.v file:

'timescale 1ns / 1ps

module Mux4to1(output [4:0] out, input [3:0] in, [1:0] sel);
assign  out = sel[1] ? (sel[0] ? in[3] : in[2]) : (sel[0] ? in[1] : in[0]);
// if s1 is high, then evaluate first s0 block
// if s1 is low, evaluate second s0 block
// second "nested" ternary operation decides which input is high and passes
// it along to output.
endmodule

module Mux16to1 (output [15:0] out, input [15:0] in, input [3:0] sel);
wire [4:1] k;

Mux4to1 mux0(k[1], in[3:0], sel[1:0]);
Mux4to1 mux1(k[2], in[7:4], sel[1:0]);
Mux4to1 mux2(k[3], in[11:8], sel[1:0]);
Mux4to1 mux3(k[4], in[15:12], sel[1:0]);
Mux4to1 mux4(out, k[4:1], sel[3:2]); // overall 16to1mux output

endmodule



testbench code to test two outputs:

timescale 1ns / 1ps

module testbench;
reg [15:0] in = 0;
reg [3:0] sel = 0;
wire [15:0] out;

// UUT
Mux16to1 mux(out,in,sel);

initial
begin

\$monitor("in=%b | sel=%b | out=%b",
in,sel,out);

end

initial
begin

in=16'b0000000000000000; sel=4'b0000;
#30 in=16'b0000000000000001; sel=4'b0000;

end
endmodule


For my second combinational input, I am expecting my output to be 0000000000000001. I believe this should be the output due to sel passing the least significant bit of my input. However, this is not the case. My testbench reads output as "ZZZ1", here:

I am not sure what I am doing incorrectly. After reading that High Z typically means some ports are not connected, I feel as if I did my instantiation incorrectly. What am I missing here?

## 1 Answer

I have realized my problem. I misunderstood how the output for a mux should be structured.

In a 4to1 mux, the ratio for inputs:outputs is 4:1. Similarly, a 16to1 mux will have the same ratio. Therefore, we should only expect 4 binary digits as output.

This is why the 3 most significant outputs were High Z. They were not connected to anything. Changing [15:0] out to [3:0] out has solved my problem.

• The outputs for Mux4to1 and Mux16to1 Should be single bit (output out`) as the upper bits will always be zero.
– Greg
Sep 5, 2021 at 16:16