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As far as I know, 2 synchronize used to be used in in asynchronous FIFO for preventing metastability in multi clock domain. as the below, cross clock domain databus

But I came across about Metastability is "The gray encoding is used to prevent race conditions from CDC, not prevent metastability." and I can find good posting in What is metastability?

So I'm confused that I thought that Metastability is caused by setup-hold timing violation. and also it happens in CDC domain. Usually, to prevent x propagation problem in CDC domain eventually we use 2 stage flip-flop.

Could you guide me for understand between "2 synchronize" and "metastability"?

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    \$\begingroup\$ "2 synchronize" is to "metastability" as "vaccine" is to "infection". One is a method for preventing the other. \$\endgroup\$ Sep 5, 2021 at 16:32
  • \$\begingroup\$ Added a metastability tag. Thar’s gold in them thar hills… \$\endgroup\$ Sep 5, 2021 at 16:42
  • \$\begingroup\$ 2 stage synchroniser protects against far more than metastability, which is a tiny portion of the race condition problem. \$\endgroup\$
    – user16324
    Sep 5, 2021 at 16:46

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The two are applied entirely differently.

Metastability applies to any signal line which is being digitally sampled. If a transition occurs too close to the sample time, the output of the sample device (normally a flip-flop) can become metastable. That is, it may enter an intermediate state for a hopefully brief time.

Adding a 2nd sampling device which samples the first after a significant period can also produce a metastable state. But the odds on that much smaller, since the first device has been given time to settle out of its metastable state. For real devices, it's not hard to produce a 2-step process with MUCH better reliability than a single stage. In some cases, adding additional stages may be a good idea.

Grey code / race conditions applies to parallel codes which require multiple lines. It's also known as skew. Let's say you have a 4-bit code which transitions from 0111 (decimal 7) to 1000 (decimal 8). If the most significant bit arrives slightly before the other three, the receiver will see 0111 followed briefly by 1111, then the correct value of 1000. As you can imagine, this is not a Good Thing.

Grey codes address the question by replacing a "normal" binary progression with one which only changes a single bit from value to value. This will take more bits for the same dynamic range, but that can be an acceptable tradeoff, depending on system design. For instance, if the data source provides synchronous data, it can also provide a clock to provide arrival timing of the new code, avoiding skew problems entirely.

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Metastability is caused by setup-hold timing violation.

That is absolutely right as far as the clock referenced signals are concerned.

Meantime, Gray code is, on WikiPedia

an ordering of the binary numeral system such that two successive values differ in only one bit (binary digit).

Thus, it gives various advantages over plain weighted-binary (natural binary) code, although it depends on the applications; glitch, signal band-width, error detection and correction.

Thus, gray code can benefit to serial data, parallel data, registered/clocked data, and/or combinatorial logic data, but not only limited to error resolution of CDC meta-stability.

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When re-synchronizing a group of signals (like a FIFO pointer) from one clock domain to another, if more than one bit changes at a time, the synchronizer could miss some of the changing bits because of unequal delays of each bit.

Using Gray coding avoids this by only allowing one bit at a time to change state. Then there will be no case of the synchronizer missing bit state changes due to a mismatch in timing, which would happen if the non-Gray version were used.

In other words, Gray coding is a workaround for a side-effect that’s introduced by the synchronizer flip-flops that deal with the metastability issue.

What is metastability, anyway? It’s the case where the flip-flop has entered an in-between state, where it hasn’t snapped to a valid ‘1’ or ‘0’ yet. It’s balanced as if on a very narrow knife edge, and will eventually be nudged one way or another by some random noise in the circuit. In the absence of that noise it could sit there indefinitely; in real systems these events last a few nanoseconds.

So we use two flip-flops to fix metastability. Why? It’s based on the statistical improbability that both flip-flops in a row will fail to resolve to a valid state. The two flip-flop synchronizer doesn’t completely eliminate metastability, but done correctly, makes it statistically so rare that it’s no longer an issue.

More here: How does 2-ff synchronizer ensure proper synchonization?

And here: Why do cascading D-Flip Flops prevent metastability?

And try the ‘metastability’ tag that I added.

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