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I know, implementing the TCP/IP stack in hardware on a FPGA is a very difficult task and should be done in software. My goal is, only to implement the necessary parts of the stack on hardware so I can send TCP packets from the FPGA to a computer where the full stack is implemented (e.g. Windows or Linux). I don't need bidirectional communication, unidirectional FPGA -> PC is completely fine and the only important thing I want is the retransmit if a package is missing or timing out. The MAC and IP address of the FPGA as well the PC are known. I found this paper describing such a method, but unfortunately without any code examples.

Now my question: Is it possible to reduce the TCP/IP stack in that way, that a implementation on a FPGA is possible that doesn't take too much time? What is the best approach to solve this problem if I want to start with only sending the TCP header that I can analyze it with Wireshark?

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    \$\begingroup\$ TCP necessarily involves bidirectional communication, even if only one end sends payload. \$\endgroup\$
    – TypeIA
    Sep 6 at 15:30
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    \$\begingroup\$ Usually the tcp stack is still implemented software, with a microprocessor in the fpga. Find a dev board with Ethernet on it \$\endgroup\$
    – Voltage Spike
    Sep 6 at 15:31
  • \$\begingroup\$ Welcome to the site. My personal opinion: It is possible, but I would try something else, more efficient architecture. First problem I see is not only the client, but the server side will need 5x (for 5 clients) faster front end + super fast processor. Quote from the material: 1) we designed a simplified and unidirectional version of the protocol. 2) For protocol verification and testing we developed an emulator. 3)Testbed configuration for congestion control verification. The five sender PCs are running the simplified TCP emulator, the receiver PC is running standard Linux TCP/IP stack. \$\endgroup\$
    – jay
    Sep 6 at 16:49
  • \$\begingroup\$ You won't even easily find a standardized IP Core of TCP/IP stack cz nobody does that. \$\endgroup\$
    – Mitu Raj
    Sep 6 at 18:33
  • \$\begingroup\$ Instead of TCP, you might want to build your own protocol on top of UDP. You can add an acknowledgement/retry system to the protocol and it can be simpler than TCP. \$\endgroup\$
    – user253751
    Sep 7 at 16:25
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Your minimalist TCP/IP implementation in an FPGA may be a soft core processor running some code.

The bare essence of this is that TCP/IP requires a big and (relatively) slow state machine. In general, you make efficient use of logic (compared to a processor) if you're implementing (relatively) small and fast state machines, or better yet, arithmetic that just pipelines through without any explicit state at all.

State machines (or algorithms) that are big and slow with respect to the speed and size of the logic are perfect candidates for shoving into a processor. Logic does what it does well, processors do what they do well, and processors, with their small logic cores and oceans of cheap memory, tend to do "big and slow" quite well.

If you do a naive implementation of the state machine in logic (i.e., states in registers, with sections of logic that only light up when "their" state is active), then you'll use up a lot of logic that you could have used for other things. Most of your logic will be sitting idle, waiting for something to happen, taking up space and (in an FPGA) burning up power.

I would suggest that you go ahead and build a strawman implementation of TCP/IP in logic. Then look at how much logic you're using. Then select a processor core that uses about half that much logic, and assess whether it can be used to implement a TCP/IP stack in its software. Or select the smallest-size processor core that can implement a TCP/IP stack, and compare that to your TCP/IP-in-logic strawman.

Then, make your decision.

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    \$\begingroup\$ you could also end up using a big table to drive your state machine and reuse logic, which makes it essentially a processor. \$\endgroup\$
    – user253751
    Sep 7 at 16:26
  • \$\begingroup\$ @user253751: yes; I considered mentioning that, but as you said, one is basically building a one-purpose processor at that point. These days it's probably better to obtain someone's general-purpose processor IP that's been optimized. \$\endgroup\$
    – TimWescott
    Sep 7 at 23:16
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You can have a look at FPGA Cores. They do Ethernet cores with TCP and more without processor. Maybe you can get some ideas from that. I have used them in several projects. Probably Xilinx only. They are free to download. Cheers.

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